The invention relates to a method and a corresponding arrangement for sequencing at least two biopolymers (6), wherein for each biopolymer (6) a sequence signal is picked up by a respective measured variable pickup on the basis of the sequence of the biopolymer (6), the sequence signals are transferred to a shift register (16) and buffer-stored therein, the buffer-stored sequence signals are transferred from the shift register (16) sequentially to an evaluation device (26) and evaluated therein. Each sequence signal is preferably produced here by means of a nanopore arrangement (10). A corresponding sequencing arrangement (11) has the measured variable pickups and the shift register (16) integrated in it, preferably in an electrical circuit, that is to say on a sensor array, for example. Each sequence signal can be amplified here by a preamplifier (14) prior to transfer to the shift register (16). The transfer of the output signal (A) to the evaluation device (24) can comprise the amplification of the signal by an output amplifier (24) and/or at least one EMCCD stage (32).

The invention relates to a method and a corresponding arrangement for sequencing at least two biopolymers (6), wherein for each biopolymer (6) a sequence signal is picked up by a respective measured variable pickup on the basis of the sequence of the biopolymer (6), the sequence signals are transferred to a shift register (16) and buffer-stored therein, the buffer-stored sequence signals are transferred from the shift register (16) sequentially to an evaluation device (26) and evaluated therein. Each sequence signal is preferably produced here by means of a nanopore arrangement (10). A corresponding sequencing arrangement (11) has the measured variable pickups and the shift register (16) integrated in it, preferably in an electrical circuit, that is to say on a sensor array, for example. Each sequence signal can be amplified here by a preamplifier (14) prior to transfer to the shift register (16). The transfer of the output signal (A) to the evaluation device (24) can comprise the amplification of the signal by an output amplifier (24) and/or at least one EMCCD stage (32).

The present disclosure provides a shift register unit whose operating time includes a plurality of multi-frame periods, each of the multi-frame periods including a plurality of frame periods. The shift register unit includes a trigger signal input terminal, an input circuit, a pull-up circuit, a pull-down control circuit, a plurality of pull-down circuits, and a signal output terminal. The pull-down control circuit is configured to sequentially provide active signals to the control terminals of respective pull-down circuits in pull-down stages of respective frame periods of one multi-frame period. The present disclosure further provides a shift register, a gate driving circuit and a display panel.

The present disclosure provides a shift register unit whose operating time includes a plurality of multi-frame periods, each of the multi-frame periods including a plurality of frame periods. The shift register unit includes a trigger signal input terminal, an input circuit, a pull-up circuit, a pull-down control circuit, a plurality of pull-down circuits, and a signal output terminal. The pull-down control circuit is configured to sequentially provide active signals to the control terminals of respective pull-down circuits in pull-down stages of respective frame periods of one multi-frame period. The present disclosure further provides a shift register, a gate driving circuit and a display panel.

A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.