Digital circuits, and other types of circuits, may be implemented using improved charge domain techniques based on modern silicon processing compatible with standard digital flows. An example of technology that can be used for charge domain digital flows are FINs (as used in FinFET) which can be modified to produce charge domain shift registers and charge domain digital logic. Also, novel notch based implementations which overcome limited potential range, speed, complex clocking and density issues of older generations of charge domain technology may be disclsoed. Such implementations can significantly improve performance, density and reduce power consumption of charge domain digital circuits, with the proper implants and process modifications.

A flexible display panel and a driving method thereof, and a display device are provided. The flexible display panel includes a pixel region and a gate driving circuit region located outside the pixel region. The flexible display panel further includes a curvature adjusting unit located on two sides of the pixel region, the curvature adjusting unit includes a plurality of isosceles trapezoid units which are sequentially connected with each other through lower surfaces thereof, each isosceles trapezoid unit includes an upper surface, the lower surface, and a third waist surface and a fourth waist surface oppositely arranged between the upper surface and the lower surface, and a length of the upper surface between the third waist surface and the fourth waist surface is less than a length of the lower surface between the third waist surface and the fourth waist surface. In the case that the display panel is bent and in a bent portion of the display panel, the third waist surface of the isosceles trapezoid unit attaches to the fourth waist surface of the isosceles trapezoid unit adjacent thereto, and the upper surface of the isosceles trapezoid unit is connected with the upper surface of the isosceles trapezoid unit adjacent thereto.

A flexible display panel and a driving method thereof, and a display device are provided. The flexible display panel includes a pixel region and a gate driving circuit region located outside the pixel region. The flexible display panel further includes a curvature adjusting unit located on two sides of the pixel region, the curvature adjusting unit includes a plurality of isosceles trapezoid units which are sequentially connected with each other through lower surfaces thereof, each isosceles trapezoid unit includes an upper surface, the lower surface, and a third waist surface and a fourth waist surface oppositely arranged between the upper surface and the lower surface, and a length of the upper surface between the third waist surface and the fourth waist surface is less than a length of the lower surface between the third waist surface and the fourth waist surface. In the case that the display panel is bent and in a bent portion of the display panel, the third waist surface of the isosceles trapezoid unit attaches to the fourth waist surface of the isosceles trapezoid unit adjacent thereto, and the upper surface of the isosceles trapezoid unit is connected with the upper surface of the isosceles trapezoid unit adjacent thereto.

There is provided a transmission apparatus including: a shift register configured to generate a plurality of timing pulses indicating different timings, from a frame pulse synchronized with a frame signal; and a plurality of signal processors configured to sequentially process the frame signal based on timings indicated by one or more timing pulses among the plurality of timing pulses.

A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

The invention is notably directed to a method of processing data. The method relies on a memory device having a crossbar array structure. The latter includes KL cells, which interconnect K rows and Z columns. The cells include respective memory systems, which store respective A-bit weights. The memory systems are connected to respective compute units, which are configured as interleaved switched-capacitor analogue multipliers and adders. According to the proposed method, input signals encoding respective M-bit input words are synchronously applied to respective ones of the K rows. The compute units are operated according to a 3-phase clocking scheme, with a view to obtaining MAC results for each of the L columns, where K2, L>2, N2, and M2. Remarkably, the 3-phase clocking scheme is here set to perform nm partial multiplications, in the analogue domain, according to a specific bit partition, so as to obtain nm partial output signals in output of each of the compute units. This partition decomposes each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits. Each of the n groups and the m groups includes at least one bit. However, at least one of the n groups and/or the m groups includes at least two bits, whereby N+M>n+m3. Moreover, the MAC results are obtained by summing the partial output signals obtained by the compute units for each of the Z columns. The summed output signals are converted into digital signals encoding partial values. The partial values are shifted according to corresponding bit positions, which are set in accordance with the bit partition, and the shifted values are finally added, so as to recompose the desired output vector components. The invention is further directed to related apparatuses and systems.

The invention is notably directed to a method of processing data. The method relies on a memory device having a crossbar array structure. The latter includes KL cells, which interconnect K rows and Z columns. The cells include respective memory systems, which store respective A-bit weights. The memory systems are connected to respective compute units, which are configured as interleaved switched-capacitor analogue multipliers and adders. According to the proposed method, input signals encoding respective M-bit input words are synchronously applied to respective ones of the K rows. The compute units are operated according to a 3-phase clocking scheme, with a view to obtaining MAC results for each of the L columns, where K2, L>2, N2, and M2. Remarkably, the 3-phase clocking scheme is here set to perform nm partial multiplications, in the analogue domain, according to a specific bit partition, so as to obtain nm partial output signals in output of each of the compute units. This partition decomposes each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits. Each of the n groups and the m groups includes at least one bit. However, at least one of the n groups and/or the m groups includes at least two bits, whereby N+M>n+m3. Moreover, the MAC results are obtained by summing the partial output signals obtained by the compute units for each of the Z columns. The summed output signals are converted into digital signals encoding partial values. The partial values are shifted according to corresponding bit positions, which are set in accordance with the bit partition, and the shifted values are finally added, so as to recompose the desired output vector components. The invention is further directed to related apparatuses and systems.

A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

The invention is notably directed to a method of processing data. The method relies on a memory device having a crossbar array structure. The latter includes KL cells, which interconnect K rows and Z columns. The cells include respective memory systems, which store respective A-bit weights. The memory systems are connected to respective compute units, which are configured as interleaved switched-capacitor analogue multipliers and adders. According to the proposed method, input signals encoding respective M-bit input words are synchronously applied to respective ones of the K rows. The compute units are operated according to a 3-phase clocking scheme, with a view to obtaining MAC results for each of the L columns, where K2, L>2, N2, and M2. Remarkably, the 3-phase clocking scheme is here set to perform nm partial multiplications, in the analogue domain, according to a specific bit partition, so as to obtain nm partial output signals in output of each of the compute units. This partition decomposes each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits. Each of the n groups and the m groups includes at least one bit. However, at least one of the n groups and/or the m groups includes at least two bits, whereby N+M>n+m3. Moreover, the MAC results are obtained by summing the partial output signals obtained by the compute units for each of the Z columns. The summed output signals are converted into digital signals encoding partial values. The partial values are shifted according to corresponding bit positions, which are set in accordance with the bit partition, and the shifted values are finally added, so as to recompose the desired output vector components. The invention is further directed to related apparatuses and systems.