A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines.

A memory system having a mode indicator, a set of hardware resources, a set of media, and a controller. When the mode indicator identifies a factory mode, a first portion of the hardware resources is reserved for performance of factory functions by the controller and a second portion of the hardware resources is allocated for performance of normal functions. When the mode indicator identifies a user mode, both the first portion and the second portion are allocated for the performance of the normal function. The normal functions are performed by the controller to at least store data in and retrieve data from the set of media in response to requests from a host system.

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

Methods, systems, and devices for defect detection for a memory device are described. A segmented digital die defect detector may include multiple signal lines, each coupled with a test circuit, and a control circuit to form a path. At least part of the path may extend through an internal portion of the die. A test circuit may generate a digital feedback signal that indicates a condition of a respective signal line. The control circuit may generate a single output signal, indicative of the condition of the signal lines. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die defect detector may be reduced and a power consumption associated with the testing operation may be reduced.

A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.

Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.

Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a wordline driving circuit including a plurality of sub-wordline decoders respectively connected to the plurality of wordlines, wherein each of the sub-wordline decoders is configured to input a first driving signal to the respectively connected wordline when the wordline is selected, and wherein each sub-wordline decoder is configured to input a predetermined power supply voltage to the respectively connected wordline when the wordline is unselected, The memory device may include a sense amplifier circuit including sense amplifiers connected to the bitlines, and a logic circuit configured to determine a failure of at least one of the memory cell array and the wordline driving circuit.