A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

A method for obtaining circuit noise parameters and an electronic device are provided. The method includes: determining a plurality of circuits to be tested, where each circuit includes one or more signal lines, and each circuit has at least one operating state; obtaining a parasitic capacitance between each signal line and all others signal lines, and determining a logic state of each signal line under each of the operating states; determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance.

A test method and a test system are provided. The method includes that: first initial data is written into the storage module; ECC module encodes and generates first check data corresponding to first initial data based on first initial data, and writes first check data into the storage module; second initial data is written into a same address of the storage module; second initial data and first check data in the storage module are read. ECC module encodes and generates second check data corresponding to second initial data based on second initial data, and checks and corrects second initial data based on the first check data and the second check data; first read data of the memory is read, and whether a function of ECC module is abnormal is determined based on the first read data, the first read data is checked and corrected second initial data.

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

The present disclosure provides a method for determining status of a fuse element of a memory device. The method includes providing the memory device including a first terminal and a second terminal and applying a first power signal on the first terminal of the semiconductor device. The memory device includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

A word line control method, a word line control circuit device, and a semiconductor memory are provided. The method includes: acquiring a row address input signal; acquiring a test mode signal; performing logical and decoding operations on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals; and simultaneously activating at least two non-adjacent word lines based on the at least two valid activation signals. The row address control signal obtained allows simultaneous activation of at least two non-adjacent word lines. Since none of any two non-adjacent word lines share a common contact area, a test will not be affected by the disconnection of a contact area or the presence of high impedance, thus improving test accuracy.