A method of operating a nonvolatile memory system including a memory device having a plurality of memory blocks includes selecting a source block among the plurality of memory blocks in the nonvolatile memory system, and performing a reclaim operation for the source block based on the number of program and erase cycles which have been performed on the source block.

A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.

A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.

According to an embodiment, when a storage status of a first storage unit is recognized as a protected state, a control unit writes data to a second storage unit. When a read target address is recorded in a data migration log area, the control unit reads data from the second storage unit. When the read target address is not recorded in the data migration log area, the control unit reads data from the first storage unit.

Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.

Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.

Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.

Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.