Disclosed is a nonvolatile memory device which includes a memory cell array, a row decoder circuit that selects one wordline as a target of a program operation, a page buffer circuit that stores data to be written in memory cells connected with the selected wordline in the program operation, and a pass/fail check circuit that determines a pass or a fail of the program operation. In the program operation, the pass/fail check circuit detects a first program speed of first memory cells and a second program speed of second memory cells, and determines a program fail based on the first program speed and the second program speed.

An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.

A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.

A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

Disclosed herein are components of an emulation system capable of efficiently recreating the functionality a CAM/TCAM memory circuit. Rather than using specialized gates or the existing processors, the embodiments described herein configure/instruct the existing memory circuits of the emulation system to imitate a search engine function that queries the existing RAM circuits, portions of which are reconfigured to function as CAM/TCAM memory. The hardware-based search engine and the repurposed memory (e.g., RAM, SRAM, DRAM) allow an emulation system to emulate the functionality of a CAM/TCAM memory. This can be implemented at a low processing cost to the emulation system, as it provides the ability to store more CAM/TCAM data at a very low cost. It can also use the existing system and emulation buses that other components (e.g., processors) of the system use to communicate with the memory, so expansion of the emulation system may not be required.