Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.

Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.

Techniques are provided for writing a high-level state to a memory cell capable of storing three or more logic states. After a sense operation performed by a first sense component and a second sense component, a digit line may be isolated from the first sense component and the second sense component. The high-level state may be stored in the memory cell, then a second state may be stored in the memory cell, in which the second state may be a mid-level state or a low-level state. The second state may be stored based on a write-back component identifying that the second state was stored in the memory cell before the write back procedure.

A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.

Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.

Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.

A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.