Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.

According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, and a sense amplifier. The sense amplifier includes: a first node configured to be electrically coupled to the bit line; a first transistor in which a gate is coupled to the first node, and which is configured to be coupled to a second node; a second transistor configured to couple the second node and a third node; and a third transistor in which a gate is coupled to the third node, and which is configured to be coupled to the first node. The sense amplifier applies a second voltage obtained by amplifying a first voltage of the first node to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node.

The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.

Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.

According to one embodiment, a memory device includes a memory cell array; a generation circuit generating a reference current; a sense amplifier comparing a cell current flowing through a memory cell with the reference current; a first clamp transistor connected between the sense amplifier and the memory cell; a second clamp transistor connected between the sense amplifier and the generation circuit; a first interconnect layer connected to a gate of the first clamp transistor; a second interconnect layer connected to a gate of the second clamp transistor and arranged adjacent to the first interconnect layer; and a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer, a fixed voltage being applied to the first shield line.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.

A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.