Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.

A resistive memory device is provided. The resistive memory device includes a bitline, a source line, a memory cell electrically connected to the bitline and the source line by a first switch, a first transistor electrically connected to the bitline, a second transistor electrically connected to the source line, a gate voltage generator configured to generate a first gate voltage that is provided to a gate electrode of the first transistor, and configured to generate a second gate voltage that is provided to a gate electrode of the second transistor and a second switch that provides the first and second gate voltages to the gate electrodes of the first and second transistors.

A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.

A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.