G11C2207/007

Longest element length determination in memory
10984841 · 2021-04-20 · ·

A length of a longest element can be determined in a memory device. An example method includes determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array. The determination of the length of the longest element can include performing a number of AND operations, shift operations, and invert operations.

MULTI-BUFFERED REGISTER FILES WITH SHARED ACCESS CIRCUITS

Systems, apparatuses and methods identify a plurality of registers that are associated with a system-on-chip. The plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations. The technology writes data to the first portion of the plurality of registers, and transfers the data from the first portion to the second portion.

System and method for cryogenic hybrid technology computing and memory

A system and method for high-speed, low-power cryogenic computing are presented, comprising ultrafast energy-efficient RSFQ superconducting computing circuits, and hybrid magnetic/superconducting memory arrays and interface circuits, operating together in the same cryogenic environment. An arithmetic logic unit and register file with an ultrafast asynchronous wave-pipelined datapath is also provided. The superconducting circuits may comprise inductive elements fabricated using both a high-inductance layer and a low-inductance layer. The memory cells may comprise superconducting tunnel junctions that incorporate magnetic layers. Alternatively, the memory cells may comprise superconducting spin transfer magnetic devices (such as orthogonal spin transfer and spin-Hall effect devices). Together, these technologies may enable the production of an advanced superconducting computer that operates at clock speeds up to 100 GHz.

Elastic cosmetic masks and methods for treating skin
10940103 · 2021-03-09 · ·

The instant disclosure relates to masks, methods for making masks, methods for improving film elasticity of masks, and to methods of treating skin with masks. The masks are formed by applying a mask base composition onto a surface, the mask base composition comprising: (i) alginic acid and/or a salt thereof; (ii) hectorite (lithium magnesium sodium silicate); (iii) one or more water-soluble solvents; and (iv) water; and exposing the mask base composition to a crosslinking composition for a time sufficient to crosslink the alginic acid and/or a salt thereof and form a final mask, the crosslinking composition being an aqueous liquid comprising (i) one or more polyvalent cations of one or more metals; and (ii) water. The instant disclosure further relates to masks formed by the disclosed methods and to kits comprising the compositions for making and/or using the masks.

Flip flop standard cell

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

LONGEST ELEMENT LENGTH DETERMINATION IN MEMORY
20200219544 · 2020-07-09 ·

Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

Multi-port register file device and method of operation in normal mode and test mode
10706949 · 2020-07-07 · ·

A storage device includes: a first disabling unit configured to output write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by a first holding unit do not match; a second holding unit configured to hold sets of the plurality of write addresses held by the first holding unit and the plurality of write enable signals output by the first disabling unit; a second disabling unit configured to output one write enable signal of the plurality of write enable signals held by the second holding unit without change in a test mode; and a third holding unit configured to write data in accordance with sets of the plurality of write addresses held by the second holding unit and the plurality of write addresses output by the second disabling unit.

Counter design with various widths for image sensor

Counters with various widths for an image sensor. An image sensor includes a plurality of image pixels arranged in rows and columns of a pixel array. A plurality of memory cells are individually coupled to corresponding columns of the pixel array. The memory cells are arranged in a memory bank. The memory bank includes a first memory cell coupled to a first column of the pixel array. The first memory cell includes a first counter having a first width. A second memory cell is coupled to a second column of the pixel array. The second memory cell comprises a second counter having a second width. The first width and the second width are different.

Longest element length determination in memory
10593376 · 2020-03-17 · ·

Apparatuses and methods determine a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

FLIP FLOP STANDARD CELL
20200059223 · 2020-02-20 ·

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.