A semiconductor memory device includes: a plurality of banks having a data storage unit and an error correction code storage unit; an error correction code generation unit; an error correction unit; a row counter that determines a row address as a refresh target; a bank counter that determines a bank address as an error correction target; and a column counter that determines a column address as the error correction target. The error correction unit performs the error correction process on a data of an error correction target address determined based on the row counter, the bank counter, and the column counter when receiving a refresh command.

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. The amplification unit may be configured to amplify a voltage difference between the read reference voltage with the voltage level of the global bit line. The pass transistor may be configured to transfer a current from the sensing node to the global bit line based on a signal output from the amplification unit. The latch unit may be configured to generate an output signal by detecting a voltage level change of the sensing node.

A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the sense amplifier; a recycling arrangement selectively connectable to the branched line; an array of bit lines connected to corresponding memory cells; a multiplexer configured to selectively connect the branched line to a selected one of the memory cells through a corresponding line amongst the array of bit lines; and a controller. The controller is configured to: permit, during a recovery phase in which a gleaned amount of charge (gleaned charge) is recovered, flow of charge (charge-flow) between the recycling arrangement and the branched line; interrupt, during a drainage phase in which the gleaned charge is preserved, charge-flow between the recycling arrangement and the branched line; and permit, during a reuse phase in which the gleaned charge is reused, charge-flow between the recycling arrangement and the branched line.

Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

Methods, systems, and devices for a clamping circuit for an amplifier circuit in a memory system are described. The amplifier circuit may be configured to amplify a difference between a first voltage conveyed by a first input node and a second voltage conveyed by a second input node, the first voltage associated with a state of a memory cell. The clamping circuit may be configured to halt amplification by the amplification circuit by modifying a voltage of a gate terminal of a transistor of the amplifier circuit.