An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes one or more first equalization transistors proximate the first and second regions, and includes a second equalization transistor proximate the SENSE AMPLIFIER circuitry. Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes an electrical connection coupling the first and second regions to one another.

Apparatuses and methods can be related to countering noise at a memory array. Countering noise can include enable switches to connect third digit lines of the first array adjacent to the respective first digit lines to fourth digit lines of the second array adjacent to the reference digit lines such that the reference digit lines experience a same amount of digit line coupling noise as the first digit lines experience.

Apparatuses and methods can be related to countering noise at a memory array. Countering noise can include enable switches to connect third digit lines of the first array adjacent to the respective first digit lines to fourth digit lines of the second array adjacent to the reference digit lines such that the reference digit lines experience a same amount of digit line coupling noise as the first digit lines experience.

A pre-charge circuit of a static random access memory (SRAM) controller and a pre-charging method thereof are provided. The pre-charge circuit of the SRAM controller includes a first switch, a second switch and a third switch. A first terminal of the first switch is coupled to a working voltage, a second terminal of the first switch is coupled to a first bit line of the SRAM controller, and the first switch is controlled by a first turn-on signal. A first terminal of the second switch is coupled to the working voltage, a second terminal of the second switch is coupled to a second bit line of the SRAM controller, and the second switch is controlled by a second turn-on signal. The third switch is coupled between the first bit line and the second bit line, and the third switch is controlled by a third turn-on signal. In a pre-charge mode, a time point at which the third switch is turned on is earlier than a time point at which the first switch is turned on and earlier than a time point at which the second switch is turned on.

A pre-charge circuit of a static random access memory (SRAM) controller and a pre-charging method thereof are provided. The pre-charge circuit of the SRAM controller includes a first switch, a second switch and a third switch. A first terminal of the first switch is coupled to a working voltage, a second terminal of the first switch is coupled to a first bit line of the SRAM controller, and the first switch is controlled by a first turn-on signal. A first terminal of the second switch is coupled to the working voltage, a second terminal of the second switch is coupled to a second bit line of the SRAM controller, and the second switch is controlled by a second turn-on signal. The third switch is coupled between the first bit line and the second bit line, and the third switch is controlled by a third turn-on signal. In a pre-charge mode, a time point at which the third switch is turned on is earlier than a time point at which the first switch is turned on and earlier than a time point at which the second switch is turned on.

A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.

A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplayer circuit (140) comprises, for each bit line, an associated NMOS (142a, 142b) device that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit (150) when activated by a corresponding bit line selection signal, and a multiplex controller (144) that is configured to be able to select each pair of bit lines by activating the associated NMOS devices (142a, 142b) using the corresponding bit lines selection signals.

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.