According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first resistance element and a first transistor, a first bit line, a second transistor, and a sense circuit. The memory cell and the first circuit are connected to the first bit line. One end and the other end of the second transistor are connected to the first bit line and the sense circuit respectively. During a first operation before reading data of the memory cell a voltage of the first bit line falls to a first voltage and the first and second transistors are turned off in response to a fall of the voltage of the first bit line to the first voltage.

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

A system and method for efficient power, performance and stability tradeoffs of memory accesses are described. A memory includes an array of cells for storing data and a sense amplifier for controlling access to the array. The cells receive word line inputs for data access driven by a first voltage supply. The sense amplifier includes first precharge logic, which receives a first precharge input driven by the first power supply used by the array. Therefore, the first precharge input has similar timing characteristics as the word line input used in the array. The sense amplifier includes second precharge logic, which receives a second precharge input driven by a second power supply not used by the array and provides precharged values on bit lines driven by the second power supply.

A system and method for efficient power, performance and stability tradeoffs of memory accesses are described. A memory includes an array of cells for storing data and a sense amplifier for controlling access to the array. The cells receive word line inputs for data access driven by a first voltage supply. The sense amplifier includes first precharge logic, which receives a first precharge input driven by the first power supply used by the array. Therefore, the first precharge input has similar timing characteristics as the word line input used in the array. The sense amplifier includes second precharge logic, which receives a second precharge input driven by a second power supply not used by the array and provides precharged values on bit lines driven by the second power supply.

A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

A bit line equalizer includes a first line-shaped gate extended in a first direction, a second line-shaped gate spaced apart from the first line-shaped gate by a predetermined distance and extending parallel to the first gate, a third gate configured to interconnect the first gate and the second gate, a first contact node located at one side of the first gate, a second contact node located at one side of the second gate, a third contact node located between the first gate and the second gate and located at one side of the third gate, and a fourth contact node located between the first gate and the second gate and located at the other side of the third gate.

There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplexer circuit (140) comprises, for each bit line, an associated NMOS (142a, 142b) device that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit (150) when activated by a corresponding bit line selection signal, and a multiplexer controller (144) that is configured to be able to select each pair of bit lines by activating the associated NMOS devices (142a, 142b) using the corresponding bit line selection signals