A memory device includes a memory cell array that includes a plurality of memory cell rows, a temperature sensor that detects a temperature of the memory cell array and generates internal temperature data, a first register that stores external temperature data received from outside of the memory device, and a refresh control unit that determines a skip ratio of refresh commands received at a refresh frequency that corresponds to the external temperature data by comparing the internal temperature data and the external temperature data and performing a refresh operation for the plurality of memory cell rows in response to refresh commands skipped and transmitted based on the skip ratio.

A training controller, semiconductor device and a system including the same are disclosed, which relates to technology for training a phase of data. The training controller may include a read training circuit configured to control a read training operation based on a read signal and a control signal. The training controller may include a write training circuit configured to control a write training operation based on a write signal and a write training signal. The training controller may include a reset controller configured to generate a reset signal when a mismatch occurs in the read training operation or the write training operation.

A pre-charge system includes a pre-charge circuit and a timing controller circuit. The pre-charge circuit performs time-division pre-charge upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals, wherein the memory array includes a plurality of memory cells each coupled to one of the plurality of bit-line groups. The timing controller circuit generates and outputs the plurality of pre-charge timing control signals to the pre-charge circuit.

A receiver includes an ODT network and a signal eye sampler. The ODT network terminates a data communication interface at a selectable impedance including a nominal impedance, at least one higher impedance, and at least one lower impedance. The signal eye sampler determines an eye margin for data received on the data communication interface. The receiver selects the nominal impedance, determines a nominal eye margin associated with the nominal impedance, selects a delta impedance from one of the higher impedance and the lower impedance, determines a delta eye margin associated with the delta impedance, determines whether the delta eye margin is greater than the nominal eye margin, and sets a run time impedance value for the data communication interface to the delta impedance when the delta eye margin is greater than the nominal eye margin.

A serial read write memory is provided in which a write driver logic circuit controls a write driver to drive the bit lines in a selected column responsive to a binary value of a data in signal during a write operation in which a write mask signal is not asserted. Should the write mask signal be asserted, the write driver logic circuit controls the write driver to charge the bit line in the selected column and then to float the bit lines regardless of the binary value of the data in signal during a write operation.

A receiver includes an ODT network and a signal eye sampler. The ODT network terminates a data communication interface at a selectable impedance including a nominal impedance, at least one higher impedance, and at least one lower impedance. The signal eye sampler determines an eye margin for data received on the data communication interface. The receiver selects the nominal impedance, determines a nominal eye margin associated with the nominal impedance, selects a delta impedance from one of the higher impedance and the lower impedance, determines a delta eye margin associated with the delta impedance, determines whether the delta eye margin is greater than the nominal eye margin, and sets a run time impedance value for the data communication interface to the delta impedance when the delta eye margin is greater than the nominal eye margin.