Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

A method of operating a synapse array includes applying a pulse sequence to a resistor coupled between a row and a column of the synapse array, and in response to the applying the pulse sequence, lowering a conductance level of the resistor. Each pulse of the pulse sequence includes a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge, and applying the pulse sequence includes increasing the pulse number while increasing one of the amplitude, the pulse width, or the trailing edge duration.

An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

A battery article of manufacture comprises a plurality of components operatively associated with one another, the plurality of components comprising an electrode comprised of a material that can take up ions and discharge ions in a charging and discharging process, an electrolyte comprised of the ions, the article of manufacture also including a component comprising at least one barrier positioned between the electrolyte and the electrode, the barrier comprised of a material that substantially prevents the ions from combining with the electrode and having a structure that substantially prevents the ions from combining with the electrode, but allows the ions to travel toward or away from the electrode in the charging or discharging process.

The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.

A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.