Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

The present disclosure includes apparatuses and methods for material implication operations in memory. An example apparatus may include a plurality of memory cells coupled to a first access line and a plurality of second access lines, and a controller coupled to the plurality of memory cells. The controller of the example apparatus may be configured to apply a first signal to the first access line, and while the first signal is being applied to the first access line, apply a second signal to a first of the plurality of memory cells via another respective one of the plurality of second access lines and apply a third signal to a second of the plurality of memory cells via another respective one of the plurality of second access lines. The material implication operation may be performed as a result of the signals (e.g., first, second, and third signals) applied and a result of the material implication operation is stored on the second of the plurality of memory cells subsequent to the application of the third signal.

An integrated circuit and its manufacturing method are disclosed. The integrated circuit includes a forming voltage pad, a memory array including a plurality of memory cells, and a plurality of access lines connected to the memory cells. A forming voltage rail is coupled to the forming voltage pad. A diode is disposed in current flow communication with the forming voltage rail and an access line in the plurality of access lines. The diode is configured to be forward biased during application of a forming voltage to the forming voltage pad to induce a forming current in memory cells in the plurality of memory cells, and to be reverse biased during application of a reference voltage to the forming voltage pad during utilization of the memory array for memory operations.

Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

A computing process and product produced by the process comprises applying a write-erase cycle to a battery article of manufacture by applying a voltage controlled current source write signal to the battery in order to charge the battery, and subsequently erasing the signal by discharging the battery, where the battery comprises a plurality of components operatively associated with one another, the plurality of components comprising an electrode comprised of a material that can attract cations and repel cations in a charging and discharging process, an electrolyte operatively associated with the electrode, the electrolyte comprised of the cations the article of manufacture also including a component comprising at least one barrier component positioned between the electrolyte and the electrode, the barrier component comprised of a material and having a structure that substantially prevents the cations from combining with the electrode, but allows the cations to travel toward or away from the electrode in the charge or discharging write-erase cycle.

A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer.

A battery article of manufacture comprises a plurality of components operatively associated with one another, the plurality of components comprising an electrode comprised of a material that can take up ions and discharge ions in a charging and discharging process, an electrolyte comprised of the ions, the article of manufacture also including a component comprising at least one barrier positioned between the electrolyte and the electrode, the barrier comprised of a material that substantially prevents the ions from combining with the electrode and having a structure that substantially prevents the ions from combining with the electrode, but allows the ions to travel toward or away from the electrode in the charging or discharging process.