A three-terminal non-volatile multi-state memory device based on mobile ion induced electrical resistivity change is provided. The three-terminal non-volatile multi-state memory device-includes a substrate having a first electrode and a second electrode therein. The three-terminal non-volatile multi-state memory device further includes a mobile ion including resistor layer disposed over the first electrode, the second electrode, and part of the substrate. The three-terminal non-volatile multi-state memory device also includes a third electrode formed over the mobile ion including resistor layer. The three-terminal non-volatile multi-state memory device provides multi-level states determined by an electrical resistivity of the mobile ion including resistor layer which changes the electrical resistivity based on the mobile ton concentration in the material.

Provided is a resistance random access memory device comprising: a first electrode; a second electrode; and a metallic oxide formed between the first electrode and the second electrode. Particularly, provided is a resistance random access memory device wherein the metallic oxide comprises a first crystal grain and a second crystal grain which differ from each other in crystallographic orientation and form a boundary area; wherein a surface is intervened between the first crystal grain and the second crystal grain in the boundary area, the surface having a surface index corresponding to a surface crystallographically consisting only of oxygen among the crystal faces of the metallic oxide; and wherein the boundary area is a surface in which an electrically conductive path is formed when voltage is applied between the first electrode and the second electrode.

To provide a configuration bit circuit utilizing a phase change memory and an operation method thereof, the configuration bit circuit for a programmable logic device including a phase change memory may include a first phase change memory element and a second phase change memory element connected in series with each other between a first power source and a second power source, and a transmission gate connected to the first phase change memory element and second phase change memory element in a first direction.

A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Provided is a resistance random access memory device comprising: a first electrode; a second electrode; and a metallic oxide formed between the first electrode and the second electrode. Particularly, provided is a resistance random access memory device wherein the metallic oxide comprises a first crystal grain and a second crystal grain which differ from each other in crystallographic orientation and form a boundary area; wherein a surface is intervened between the first crystal grain and the second crystal grain in the boundary area, the surface having a surface index corresponding to a surface crystallographically consisting only of oxygen among the crystal faces of the metallic oxide; and wherein the boundary area is a surface in which an electrically conductive path is formed when voltage is applied between the first electrode and the second electrode.

A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.

Provided herein may be a data storage device. A memory device may include a plurality of memory cells; and an operation controller configured to control a word line controller and a bit line controller so that a normal write operation of applying a write voltage corresponding to a target state that is one of a set state or a reset state to the plurality of memory cells is performed, and a rewrite operation is selectively performed based on a result of the normal write operation. The rewrite operation may be an operation of providing, to the plurality of memory cells, a select voltage, having a polarity opposite to a polarity of the write voltage corresponding to the target state, and providing the write voltage corresponding to the target state.

An apparatus includes memory array having a first memory cell including a first two-terminal element having first and second threshold voltages, a second memory cell including a second two-terminal element having third and fourth threshold voltages, and a control circuit coupled to the memory array. The control circuit is configured to cause the first two-terminal element to have the first threshold voltage, and cause the second two-terminal element to have either the third threshold voltage or the fourth threshold voltage, apply a third voltage signal that increases at a first ramp rate to the first memory cell and the second memory cell, determine that the first memory cell switches from a non-conducting state to a conducting state, and read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell switches from the non-conducting state to the conducting state.

A system includes a memory array. The memory array includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of cell locations; and a plurality of cells respectively located at the plurality of cell locations. Each cell of the plurality of cells in turn includes: a first phase change memory device having a first drift; and a second phase change memory device having a second drift. The first drift is higher than the second drift.