Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

Various embodiments of the present disclosure are directed towards a memory cell including a first ferromagnetic layer and a second ferromagnetic layer. A bottom electrode via overlies a substrate. A bottom electrode overlies the bottom electrode via. A data storage layer overlies the bottom electrode. The first ferromagnetic layer overlies the data storage layer and has a first magnetization pointing in a first direction. The second ferromagnetic layer overlies the bottom electrode via and has a second magnetization pointing in a second direction orthogonal to the first direct

Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.

Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.

A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.

A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.

An OxRAM oxide based resistive random access memory cell includes a first electrode; a layer M1Oss of a sub-stoichiometric oxide of a first metal; a layer M2N of a nitride of a second metal M2; a layer M3M4O of a ternary alloy of a third metal M3, a fourth metal M4 and oxygen O, or M3M4NO of a quaternary alloy of the third metal M3, the fourth metal M4, nitrogen N and oxygen O and a second electrode. The standard free enthalpy of formation of the ternary alloy M3M4O, noted G.sub.f,T.sup.0 (M3M4O), or of the quaternary alloy M3M4NO, noted G.sub.f,T.sup.0 (M3M4NO), is strictly less than the standard free enthalpy of formation of the sub-stoichiometric oxide M1Oss of the first metal M1, noted G.sub.f,T.sup.0 (M1Oss), itself less than or equal to the standard free enthalpy of formation of any ternary oxynitride M2NO of the second metal M2, noted G.sub.f,T.sup.0 (M2NO):

G.sub.f,T.sup.0(M3M4O)<G.sub.f,T.sup.0(M1Oss)G.sub.f,T.sup.0(M2NO)

or G.sub.f,T.sup.0(M3M4NO)<G.sub.f,T.sup.0(M1Oss)G.sub.f,T.sup.0(M2NO)

A phase change memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, a rectangular array of memory pillar structures overlying top surfaces of the first conductive rails, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of memory pillar structures. Each memory pillar structure includes a vertical stack of structural elements including, from one end to another, a selector-side conductive element, a selector element, a selector-memory conductive element, a phase change memory element, and a memory-side conductive element. At least one structural element within the vertical stack is a laterally constricted structural element having laterally recessed sidewalls relative to sidewalls of a respective immediately vertically underlying structural element.