Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.

A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.

An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

Cache memory for resistive switching memory modules is provided herein. The cache memory can reside on a separate DIMM from the resistive switching memory, in some embodiments, or can share a common DIMM with the resistive switching memory. Cache management protocols are provided to service read and write policies for managing interaction of data between the cache memory and the resistive switching memory. In various embodiments, memory controllers are optimized for physical characteristics of resistive switching memory, and cache management protocols can be implemented to take advantage of these characteristics.

A storage device according to the present disclosure includes: a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, the plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines, the plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines; a first selection line driver that applies a first voltage to one or more selection lines of the plurality of first selection lines and applies a second voltage to one or more selection lines of the plurality of second selection lines, the first voltage being one of a first selection voltage and a second selection voltage, and the second voltage being one of the first selection voltage and the second selection voltage and being different from the first voltage; and a second selection line driver that applies a third voltage to one or more selection lines of the plurality of third selection lines and applies a fourth voltage to one or more selection lines of the plurality of fourth selection lines, the third voltage being one of the first selection voltage and the second selection voltage, and the fourth voltage being one of the first selection voltage and the second selection voltage and being different from the third voltage.

An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.

A neuromorphic memory circuit including a memory cell with a programmable resistive memory element. A postsynaptic capacitor builds up a leaky integrate and fire (LIF) charge. An axon LIF pulse generator activates a LIF discharge path from the postsynaptic capacitor through the resistive memory element when the axon LIF pulse generator generates axon LIF pulses. A postsynaptic comparator compares the capacitor voltage to a threshold voltage and generates postsynaptic output pulses when the capacitor voltage passes the threshold voltage. The postsynaptic output pulses include a postsynaptic firing characteristic dependent on a frequency of the axon LIF pulses. A refractory circuit prevents the postsynaptic comparator from generating additional postsynaptic output pulses until a refractory time passes since a preceding postsynaptic output pulse. A training circuit adjusts the postsynaptic firing characteristic to match a target firing characteristic.

Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.