Resistive switching memory architectures disclosed herein are capable of achieving fast read/write times and, particularly in the case of multi-bank parallel processing, executing many read or write operations per second. Because resistive switching memory is not guaranteed to be error free, resistive memory controllers can be programmed for error management when paired with such memory architectures. To reduce error management overhead, a dedicated error pin is provided to mitigate or avoid the need for a status read in conjunction with each read or write operation issued to a memory device. A status read can be implemented in response to an error signal on the dedicated error pin, but otherwise can be avoided.

Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Methods are provided for mitigating problems caused by sneak-paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: reading a value of the target memory cell; and calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an initial bits strategy or a dummy bits strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout. In addition, these strategies consume an order of magnitude less power in comparison to alternative state-of-the-art readout techniques.

For decades, advances in electronics were directly related to the scaling of CMOS transistors according to Moore's law. However, both the CMOS scaling and the classical computer architecture are approaching fundamental and practical limits. A novel memory-centric, reconfigurable, general purpose computing platform is proposed to handle the explosive amount of data in a fast and energy-efficient manner. The proposed computing architecture is based on a single physical resistive memory-centric fabric that can be optimally reconfigured and utilized to perform different computing and data storage tasks in a massively parallel approach. The system can be tailored to achieve maximal energy efficiency based on the data flow by dynamically allocating the basic computing fabric to storage, arithmetic, and analog computing including neuromorphic computing tasks.