A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.

A method for determining the junction temperature of at least one die of a semiconductor power module, the semiconductor power module being composed of plural dies connected in parallel and switching between conducting and non conductor states according to pattern cycles, the method comprises the steps of: disabling the conducting of the at least one die during at least a fraction of one switching cycle, applying a current limited voltage to the gate of the at least one die during a period of time of the cycle wherein the at least one die is not conducting, the resulting voltage excursion having a value that does not enable the die to be conducting, measuring the voltage at the gate of the die, deriving from the measured voltage a temperature variation of the junction of the at least one die or the temperature of the junction of the die.

The present disclosure discloses a temperature sensor, a display panel, and a display apparatus, in the field of sensors. The temperature sensor includes a ring oscillator consisting of n levels of phase inverters, where n is an odd number greater than or equal to 1. Each level of phase inverter includes a first thin film transistor (TFT) and a second TFT that are connected in series. An on/off state of the second TFT is configured to be in a normally-on state, an on/off state of the first TFT is configured to be determined by a signal input to the phase inverter, and mobility of an active layer material of the first TFT is greater than mobility of an active layer material of the second TFT.

An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.

An integrated circuit comprises a power switch comprising a current path and a current sense node; and a temperature sense circuit internally coupled between the current path and the current sense node.

A controller for a power converter includes an output terminal operative to output a modulation signal for controlling a phase current of the power converter. A modulator is operative to generate the modulation signal such that an output voltage of the power converter follows a first portion of a load-line when load current is above a first threshold, the first portion of the load-line having a first slope that determines a rate of change of the output voltage as a function of the load current. An interface is operative to receive a temperature signal. Circuitry is operative to change the first threshold in response to receipt of the temperature signal.

A method (50, 70, 600) provides thermal protection for an IC device that has multiple components. For each component, temperatures are sensed (51), each of which associated with a different area of the respective component and a respective temperature sense signal is output indicative of the highest sensed temperature of the respective component. For each of the components, the respective temperature sense output signal is sampled (52) to produce a sequence of discrete sampled temperature values. A sequence of differences between a reference temperature value and each of the discrete sample temperatures is integrated (53) over time to compute, for each of the components, a respective integration output. The respective integration output computed for each of the switches is compared (54) to a threshold value. An action related to the thermal protection function is initiated (55) upon the integration output of an affected component exceeding the threshold value.

A semiconductor device includes a first semiconductor element, a first signal terminal group, and a second signal terminal group disposed at an interval from the first signal terminal group. The first semiconductor element includes a control signal electrode to which a control signal for the first semiconductor element is input, and a temperature signal electrode that outputs a signal corresponding to temperature of the first semiconductor element. The temperature signal electrode is connected with a temperature signal terminal included in the first signal terminal group, and the control signal electrode is connected with a first control signal terminal included in the second signal terminal group.

A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.

The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first p-type doped region and the second p-type doped region are electrically coupled to a second potential different from the first potential.