G01R19/2506

Waveform shape discriminator
09742309 · 2017-08-22 · ·

A waveform shape discriminator includes a running maximum finder circuit coupled to receive a sense signal. The running maximum finder circuit is coupled to update a running maximum signal in response to the sense signal. A first comparator is coupled to receive the sense signal and a running maximum threshold signal that is representative of the running maximum signal. A search window block is coupled to receive the input signal to detect a search window in the sense signal. An output circuit is coupled to an output of the first comparator and an output of the search window block to determine a presence of a waveform shape in the sense signal within the search window in the sense signal.

CURRENT MEASURMENTS IN SWITCHING REGULATORS

Features and advantages of the present disclosure include a switching regulator and current measurement circuit. In one embodiment, a switching transistor in the switching regulator has a first voltage on a first terminal and a switching voltage on a second terminal. A current measurement circuit has first and second input terminals. A first switch couples the second terminal of the switching transistor to the first terminal of the current measurement circuit when the switching transistor is on, where the second input terminal of the current measurement circuit is coupled to the first terminal of the switching transistor and measurement(s) may be taken. When the switching transistor is off, the first and second input terminals of the current measurement circuit are coupled together, and measurements emulate zero current through the switching transistor.

Current Measurement for Power Converter Circuits
20220308606 · 2022-09-29 ·

A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.

ORDER O(1) ALGORITHM FOR FIRST-PRINCIPLES CALCULATION OF TRANSIENT CURRENT THROUGH OPEN QUANTUM SYSTEMS
20170219636 · 2017-08-03 ·

A fast algorithm is used to study the transient behavior due to the step-like pulse. This algorithm consists of two parts: The algorithm I reduces the computational complexity to T.sup.0N.sup.3 for large systems as long as T<N; The algorithm II employs the fast multipole technique and achieves scaling T.sup.0N.sup.3whenever T<N.sup.2 beyond which it becomes T log.sub.2 N for even longer time. Hence it is of order O(1) if T<N.sup.2. Benchmark calculation has been done on graphene nanoribbons with N=10.sup.4 and T=10.sup.8. This new algorithm allows many large scale transient problems to be solved, including magnetic tunneling junctions and ferroelectric tunneling junctions that could not be achieved before.

CURRENT DETECTION APPARATUS, CURRENT DETECTION METHOD, CURRENT CONTROL APPARATUS, AND CURRENT CONTROL METHOD
20220268814 · 2022-08-25 · ·

A current detection apparatus includes first current detection circuitry configured to detect a current flowing through a conductive wire with a shunt resistor connected to the conductive wire to obtain a first detected current value; second current detection circuitry configured to detect the current with a Hall element to obtain a second detected current value; a storage configured to store a first probability distribution information of the first current detection circuitry and a second probability distribution information of the second current detection circuitry; synthesis circuitry configured to convert the first and second detected current values into first and second probability distributions based on the first and second probability distribution information, respectively, and to synthesize the first and second probability distributions to obtain a synthesized distribution; and estimation circuitry configured to obtain an estimated current value via a maximum likelihood estimation based on the synthesized distribution.

Image rejection calibration with a passive network

In one aspect, an apparatus includes: a mixer to receive a radio frequency (RF) signal and downconvert the RF signal into a second frequency signal; an amplifier coupled to the mixer to amplify the second frequency signal; an image rejection (IR) circuit coupled to the programmable gain amplifier (PGA) to orthogonally correct a gain and a phase of the amplified second frequency signal to output a corrected amplified second frequency signal; and a complex filter to filter the corrected amplified second frequency signal.

METHOD FOR INFERRING DOWNTIME FROM POWER QUALITY DATA
20170270414 · 2017-09-21 ·

A method comprises detecting a power quality event, determining if one or more power outages occurs in a defined time period extending from a beginning of the power quality event to an end of the power quality event, and if one or more power outages occurs in the defined time period, then performing an analysis, where performing the analysis comprises determining if the one or more power outages is associated with the power quality event. The method may also comprise outputting the information regarding the analysis to a display device.

DC DETECTION CIRCUIT AND OPERATIONAL METHOD OF THE SAME, SEMICONDUCTOR APPARATUS, AND AUDIO SIGNAL OUTPUT APPARATUS
20170265000 · 2017-09-14 ·

The DC detection circuit includes: a OR circuit configured to generate a logical OR flag on the basis of logical OR of values of X bits from a (MSB-1).sup.th bit to a (MSB-X).sup.th bit of input data; a NAND circuit configured to generate a NAND flag on the basis of a NAND of values of X bits from the (MSB-1).sup.th bit to the (MSB-X).sup.th bit of the input data; a counter configured to count up and a counter value which outputs a DC detection flag if a counter value is exceeds predetermined set value on the basis of the MSB and any one of the logical OR flags of NAND flags. Accordingly, safety can be secured by detecting whether the DC data is included in the input PCM data, and thereby preventing degradation and breakage of the loudspeaker etc. due to the DC data.

Method for estimating synchrophasors during static and dynamic conditions

A method for performing synchrophasor estimation of an input signal, whereby the input signal is a sinusoidal power system voltage or current signal, comprising: a. Periodic sampling of a continuous time-domain waveform, consisting of a power system voltage or current signal, to obtain a discrete time-domain function; b. Transforming a discrete time-domain function to a discrete frequency-domain function; c. Estimating from the discrete frequency-domain function the instantaneous parameters of a synchrophasor of the sampled continuous time-domain waveform, the instantaneous parameters comprising a frequency, an amplitude and a phase angle. The method is directed to an improvement of the enhanced IpDFT-based synchrophasor estimation which takes into account interharmonic tones.

Circuit for sensing an analog signal, corresponding electronic system and method
11193952 · 2021-12-07 · ·

A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.