An eddy current displacement sensor includes devices or modules for digitizing and interpreting analog signals received from sensor coils. Periodic analog signals, such as sinusoidal or square wave signals, are sent to the coils with a suitable frequency. The output from the coils is then digitized using one or more analog-to-digital converters, at a sampling rate (frequency) that may be greater than that of the frequency of the input signal. The digitized output signals may then be processed to determine displacement of an object relative to the sensor coils, for example using magnitude and/or phase of the digital signals to estimate position. Digitizing the analog output signals directly, rather than only after such signals have been converted to DC signals, allows improvement in processing, as well as enabling flexibility in how the signals are used to estimate position.

The present invention relates to a circuit failure detector comprising: an input terminal for receiving a detection signal having a first frequency from an interlock circuit; a correction circuit for correcting the voltage of the received detection signal; a first comparator comparing the corrected detection signal with a first reference voltage and outputting a high voltage signal or a low voltage signal; a second comparator inverting the corrected detection signal, comparing the inverted detection signal with a second reference voltage, and outputting the high voltage signal or the low voltage signal; a counting signal generator for generating a counting signal having a second frequency; a first coupler for coupling an output signal of the first comparator with the counting signal; a second coupler for coupling the output signal of the second comparator with the counting signal; and a controller for detecting a circuit failure on the basis of the output signal of the first coupler and the output signal of the second coupler.

The present invention relates to a circuit failure detector comprising: an input terminal for receiving a detection signal having a first frequency from an interlock circuit; a correction circuit for correcting the voltage of the received detection signal; a first comparator comparing the corrected detection signal with a first reference voltage and outputting a high voltage signal or a low voltage signal; a second comparator inverting the corrected detection signal, comparing the inverted detection signal with a second reference voltage, and outputting the high voltage signal or the low voltage signal; a counting signal generator for generating a counting signal having a second frequency; a first coupler for coupling an output signal of the first comparator with the counting signal; a second coupler for coupling the output signal of the second comparator with the counting signal; and a controller for detecting a circuit failure on the basis of the output signal of the first coupler and the output signal of the second coupler.

A current measurement and control circuit may comprise a shunt resistor coupled between supply and output nodes; a first resistor coupled to the supply node; a second resistor coupled to ground; and a transconductance amplifier having an input coupled to the first resistor to define a compensation node and another input coupled to the output node. The circuit may also include a first transistor having a first current terminal coupled to the compensation node and a second current terminal coupled to the second resistor to define a measurement node; and a second transistor having a first current terminal coupled to ground and a second current terminal coupled to the output node. The circuit may also include an ADC having an analog input coupled to the measurement node; an IDAC having an analog output coupled to the compensation node; and switches to set the circuit in a measurement or a compensation mode.

A current measurement and control circuit may comprise a shunt resistor coupled between supply and output nodes; a first resistor coupled to the supply node; a second resistor coupled to ground; and a transconductance amplifier having an input coupled to the first resistor to define a compensation node and another input coupled to the output node. The circuit may also include a first transistor having a first current terminal coupled to the compensation node and a second current terminal coupled to the second resistor to define a measurement node; and a second transistor having a first current terminal coupled to ground and a second current terminal coupled to the output node. The circuit may also include an ADC having an analog input coupled to the measurement node; an IDAC having an analog output coupled to the compensation node; and switches to set the circuit in a measurement or a compensation mode.

The present invention relates to a system for variably controlling a sampling frequency, which facilitates the setting of sampling frequencies according to the types of various voltage/current transformers and stably collects sampling outputs of different sampling frequencies of various voltage/current transformers without collisions. The system for variably controlling a sampling frequency according to the present invention includes: a secondary converter, which collects analog data from a first sensor and converts the analog data into digital data; and a merging unit which collects analog data from a second sensor and converts the analog data into digital data while collecting the output of the secondary converter.

A current-sense ratio calibration system includes a power field effect transistor (FET) integrated circuit (IC) that includes a regulator FET to regulate current through a power path and a sense FET to provide a sense current to a sense path. The regulator FET and sense FET have an intended current-sense ratio. The system calibrates the current-sense ratio by applying proportioned stimulus signals to the power and sense paths, the proportion being the intended current-sense ratio. The calibration circuitry compares a measurement of a sense path circuit parameter made during the stimulus application to a measurement of the parameter made not during the stimulus application to derive an error term used to calibrate for any sources of error in the current-sense ratio.

A current-sense ratio calibration system includes a power field effect transistor (FET) integrated circuit (IC) that includes a regulator FET to regulate current through a power path and a sense FET to provide a sense current to a sense path. The regulator FET and sense FET have an intended current-sense ratio. The system calibrates the current-sense ratio by applying proportioned stimulus signals to the power and sense paths, the proportion being the intended current-sense ratio. The calibration circuitry compares a measurement of a sense path circuit parameter made during the stimulus application to a measurement of the parameter made not during the stimulus application to derive an error term used to calibrate for any sources of error in the current-sense ratio.

There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.

There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.