A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46 that attenuate the analog signal converted by the DA converter 3, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, and a control unit 7 that obtains a value of a step error, which is a correction value of an attenuation amount of the variable attenuators 40, 42, 44, and 46 in each of a plurality of steps obtained by dividing a maximum value of the attenuation amount of the variable attenuators 40, 42, 44, and 46 by a variation amount, which is a predetermined attenuation amount are included.

A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46 that attenuate the analog signal converted by the DA converter 3, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, and a control unit 7 that obtains a value of a step error, which is a correction value of an attenuation amount of the variable attenuators 40, 42, 44, and 46 in each of a plurality of steps obtained by dividing a maximum value of the attenuation amount of the variable attenuators 40, 42, 44, and 46 by a variation amount, which is a predetermined attenuation amount are included.

In an example, a battery management system may include a host microcontroller, which may be operated in accordance with a first clock signal; and a first analog front end (AFE) circuit. The first AFE circuit may be operated in accordance with a second clock signal that may be unsynchronized with the first clock signal. The first AFE circuit may also include first digital circuitry to (1) accumulate a first value corresponding to a number of ADC sample cycles of the first ADC, and to (2) accumulate a second value corresponding to the digital output representative of the first battery current for the ADC sample cycles accumulated in the first value. The first AFE circuit may transfer a representation of the first value and a representation of the second value to the host microcontroller in response to a request from the host microcontroller.

An integrated circuit (IC) is located on an IC chip and includes an integrated voltage regulator circuit that provides an internal supply voltage to the IC. A test mode signal can be received from an external pin of the IC chip. In response to the test mode signal, the IC can enter a test mode where the internal supply voltage is provided to components of the IC. Also in the test mode, voltage characteristics of the internal supply voltage are measured to produce an analog held value. The measurements occur in an analog domain and over a plurality of sample-and-hold windows. Upon completion of a measurement window, the analog held is converted to a digital value. The digital value is then stored in a memory circuit. The digital value is provided from the memory circuit to a reader device external to the IC.

An integrated circuit (IC) is located on an IC chip and includes an integrated voltage regulator circuit that provides an internal supply voltage to the IC. A test mode signal can be received from an external pin of the IC chip. In response to the test mode signal, the IC can enter a test mode where the internal supply voltage is provided to components of the IC. Also in the test mode, voltage characteristics of the internal supply voltage are measured to produce an analog held value. The measurements occur in an analog domain and over a plurality of sample-and-hold windows. Upon completion of a measurement window, the analog held is converted to a digital value. The digital value is then stored in a memory circuit. The digital value is provided from the memory circuit to a reader device external to the IC.

A device for measuring low currents is proposed to include: a transimpedance amplifier to convert an analog current signal into an analog voltage signal; an analog-to-digital converter to acquire a graph that plots a curve representing variation of the analog voltage signal using digital codes; a statistic module to acquire a set of crossing numbers by: for each of the digital codes, making a straight line that has a constant value equaling the digital code across time in the graph, and counting a number of crossings of the curve with the straight line; and an analysis module to analyze distribution of the crossing numbers, and to output an output code based on the distribution of the crossing numbers.

A device for measuring low currents is proposed to include: a transimpedance amplifier to convert an analog current signal into an analog voltage signal; an analog-to-digital converter to acquire a graph that plots a curve representing variation of the analog voltage signal using digital codes; a statistic module to acquire a set of crossing numbers by: for each of the digital codes, making a straight line that has a constant value equaling the digital code across time in the graph, and counting a number of crossings of the curve with the straight line; and an analysis module to analyze distribution of the crossing numbers, and to output an output code based on the distribution of the crossing numbers.

Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

In an analog-to-frequency converting circuit, a set of switches receive a first sense signal indicative of a current and provides a second sense signal that alternates between an original version of the first sense signal and a reversed version of the first sense signal, under control of a switching signal. An integral comparing circuit integrates the second sense signal to generate an integral value and generates a train of trigger signals. Each trigger signal is generated when the integral value reaches a preset reference. A compensation circuit compensates for the integral value with a predetermined value in response to each trigger signal. A control circuit generates the switching signal such that a time interval during which the second sense signal is the original version and a time interval during which the second sense signal is the reversed version are substantially the same.

An oscillator-based sensor interface circuit includes first and second input nodes arranged to receive first and second electrical signals representative of an electrical quantity, respectively; an analog filter; a first oscillator arranged to receive a first oscillator input signal and a second oscillator different from the first oscillator and arranged to receive a second oscillator input signal; a comparator arranged to compare signals coming from the first and second oscillators; a first feedback element arranged to receive a representation of the digital comparator output signal and to convert the representation into a first feedback signal to be applied to the oscillation means; a digital filter arranged to yield an output signal, being an filtered version of the digital comparator output signal; a second feedback element arranged to receive the output signal and to convert the output signal into a second feedback signal.