A phase frequency detector-based high-precision feedback frequency measurement apparatus and method: a Field Programmable Gate Array (FGPA) roughly measures a frequency fx of a measured time-frequency pulse by an equal-precision frequency measurement method; a Direct Digital Synthesizer (DDS) automatically synthesizes a frequency fx’ according to the fx roughly measured by the FPGA; the fx and the fx’ are sent to a phase frequency detector for performing phase frequency detection and then sent to the FPGA after passing through a charge pump, a low-pass filter circuit, and an (Analogue-to-Digital) A/D converter; the FPGA processes a frequency difference obtained by the phase frequency detector and then transmits the processed frequency difference to the DDS to form a negative feedback frequency measurement system so that the DDS continuously adjusts the fx’ according to a frequency difference measurement result until the output of the DDS is stable. Therefore, precise measurement of the time-frequency pulse to be measured is realized.

A phase frequency detector-based high-precision feedback frequency measurement apparatus and method: a Field Programmable Gate Array (FGPA) roughly measures a frequency fx of a measured time-frequency pulse by an equal-precision frequency measurement method; a Direct Digital Synthesizer (DDS) automatically synthesizes a frequency fx’ according to the fx roughly measured by the FPGA; the fx and the fx’ are sent to a phase frequency detector for performing phase frequency detection and then sent to the FPGA after passing through a charge pump, a low-pass filter circuit, and an (Analogue-to-Digital) A/D converter; the FPGA processes a frequency difference obtained by the phase frequency detector and then transmits the processed frequency difference to the DDS to form a negative feedback frequency measurement system so that the DDS continuously adjusts the fx’ according to a frequency difference measurement result until the output of the DDS is stable. Therefore, precise measurement of the time-frequency pulse to be measured is realized.

An oscillation period detection circuit and method, and semiconductor memory are provided. The oscillation period detection circuit includes an oscillator module, a control module, and a counting module. The oscillator module includes a target oscillator, and is configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; the control module is configured to receive the enable signal and the oscillation clock signal, and perform valid time reforming processing according to the oscillation clock signal and the enable signal to determine a target time; the counting module is configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number. The oscillation period of the target oscillator is calculated according to the target time and the target period number.

A frequency measurement circuit includes a first counter that counts a pulse number of a reference clock signal and generates first count data, a second counter that counts a pulse number of a measurement target clock signal and generates second count data, a time-to-digital conversion circuit that generates first time difference data indicating a time difference between a first timing at which the first counter starts counting of the pulse number and a second timing at which the second counter starts counting of the pulse number, and second time difference data indicating a time difference between a third timing at which the first counter ends counting of the pulse number and a fourth timing at which the second counter ends counting of the pulse number, and a calculation circuit that performs calculation based on the second count data, the first time difference data, and the second time difference data and generates frequency data indicating a frequency of the measurement target clock signal.

A frequency measurement circuit includes a first counter that counts a pulse number of a reference clock signal and generates first count data, a second counter that counts a pulse number of a measurement target clock signal and generates second count data, a time-to-digital conversion circuit that generates first time difference data indicating a time difference between a first timing at which the first counter starts counting of the pulse number and a second timing at which the second counter starts counting of the pulse number, and second time difference data indicating a time difference between a third timing at which the first counter ends counting of the pulse number and a fourth timing at which the second counter ends counting of the pulse number, and a calculation circuit that performs calculation based on the second count data, the first time difference data, and the second time difference data and generates frequency data indicating a frequency of the measurement target clock signal.

A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

A digital oscilloscope comprises a sampling unit configured to sample an input signal received from an oscilloscope probe to produce a first stream of digital samples, a first acquisition system configured to store and process the stream of digital samples to produce a first data set, a second acquisition system configured to store and process the first stream of digital samples independent of the first acquisition system to produce a second data set, and a display system configured to concurrently display the first data set in a first format and the second data set in a second format different from the first format.

Disclosed embodiments relate to sensing states and changes of states of a signal and sensors for the same, including but not limited to, autonomous sensors. Such sensor may include an analog signal threshold detection circuit, a state detection circuit, and a measurement circuit. The analog signal threshold detection circuit may be configured to alternately assert and de-assert a threshold detected indication in response to an input signal and a state thereof. The state detection circuit may be configured to generate a signal state indication about a state of the input signal. The measurement circuit may be configured to generate a measurement in response to assertions of the threshold detected indication and the signal state indication, such as a count, a slew rate, or a frequency. In some embodiments, disclosed sensors may have programmable thresholds for sensing the signal states and changes therein.

A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.