Methods and devices suitable for monitoring the frequency of microwave tunable filters in real time. The frequency readout relies on the natural response of such a filter when excited by a pulse. Methods of measuring an operating frequency of a pole in a tunable filter include measuring a number of cycles in a natural response in the filter when the filter is excited by an electric current pulse, and determining a resonance frequency based on the number of cycles measured in the natural response. Such a method can provide the operating frequency information in a binary digital format, making it relatively easy to read and process. A measuring resonator may be mounted to the filter resonator and connected by a common actuator.

The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.OSC, wherein f.sub.OSC is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.OSC, wherein f.sub.OSC is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

An analysis threshold determination device includes a threshold determination unit for determining a pair of or plural pairs of thresholds used for analysis in accordance with a pair of thresholds generated by a calculation unit and a count value output from a pulse count unit. The calculation unit repeatedly generates a new pair of thresholds in which at least one of the pair of thresholds is changed every time the pulse count unit counts the pulse until reaching a predetermined value. The threshold determination unit chooses a class of a measure of central tendency according to a frequency distribution defining each pair of thresholds generated as a class and the count value output from the pulse count unit as a frequency. The threshold determination unit determines a pair of or plural pairs of thresholds corresponding to a class of a predetermined range from the class of measure of central tendency.

An analysis threshold determination device includes a threshold determination unit for determining a pair of or plural pairs of thresholds used for analysis in accordance with a pair of thresholds generated by a calculation unit and a count value output from a pulse count unit. The calculation unit repeatedly generates a new pair of thresholds in which at least one of the pair of thresholds is changed every time the pulse count unit counts the pulse until reaching a predetermined value. The threshold determination unit chooses a class of a measure of central tendency according to a frequency distribution defining each pair of thresholds generated as a class and the count value output from the pulse count unit as a frequency. The threshold determination unit determines a pair of or plural pairs of thresholds corresponding to a class of a predetermined range from the class of measure of central tendency.

Aspects are directed to systems and methods of determining a value of a characteristic related to timing between sequential events of an input electronic signal using an input capture counter having a maximum counting value, the input electronic signal having an expected variable period between events whose value is between a maximum period value and a minimum period value with a delta period value equal to a difference between the maximum period value and the minimum period value.