In an ultra-wideband (“UWB”) communication system, methods are disclosed for transmitting packets in multiple portions, each having a different pulse repetition frequency (“PRF”). Methods are also disclosed for transmitting packets dis-continuously.

The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

In an ultra-wideband (“UWB”) communication system, methods are disclosed for transmitting packets in multiple portions, each having a different pulse repetition frequency (“PRF”). Methods are also disclosed for transmitting packets dis-continuously.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

An apparatus comprising a frequency monitor circuitry to receive a first clock signal, a second clock signal and an expected frequency ratio, determine whether a ratio between the first clock signal and the second clock signal matches an expected an expected frequency ratio and generate an error signal upon a determination that the ratio between the first clock signal and the second clock signal does not match the expected frequency ratio.

The invention relates to methods and devices for providing parameters that indicate a higher likelihood of a postoperative delirium occurring. According to a first aspect of the invention, the following steps are provided: detecting (401) at least one EEG signal at the head of the patient; determining (402) the intraoperative alpha peak frequency of the EEG signal, wherein the alpha peak frequency in the power spectrum of the EEG signal is the frequency in the alpha band for which the power is greatest; checking (403) whether the determined intraoperative alpha peak frequency is significantly lower than a predefined reference value of the alpha peak frequency; and in the event of this, providing (404) a corresponding information in the form of a parameter that shows a higher likelihood of a postoperative delirium occurring. A second aspect of the invention evaluates the change in power of the alpha band after an anesthetic-inducing drug has been administered. A third aspect of the invention relates to determining the average amplitude of the “direct current” EEG signal and the development of same on initiation of anesthetic-induced loss of consciousness.

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

A method of controlling a power supply in a multi-input power supply system includes retrieving a prior input state flag from a memory of the multi-input power supply system, determining a first dimmer input of the multi-input power supply system based on the prior input state flag, determining whether the first dimmer input is currently valid, and in response to determining that the first dimmer input is not valid, determining whether a second dimmer input of the multi-input power supply system is currently valid, and in response to determining that the second dimmer input is valid, controlling the power supply based on a second input signal received through the second dimmer input.

A method of controlling a power supply in a multi-input power supply system includes retrieving a prior input state flag from a memory of the multi-input power supply system, determining a first dimmer input of the multi-input power supply system based on the prior input state flag, determining whether the first dimmer input is currently valid, and in response to determining that the first dimmer input is not valid, determining whether a second dimmer input of the multi-input power supply system is currently valid, and in response to determining that the second dimmer input is valid, controlling the power supply based on a second input signal received through the second dimmer input.

An apparatus according to an embodiment includes a control circuit to control operations of an inverter and a switch. The control circuit judges whether or not a power system has a power failure, based on values of the system voltage and a frequency of the power system; and calculates a phase difference between a phase of the output voltage of the inverter and a phase of the system voltage and generate, by means of the phase difference, an output frequency pattern for changing a frequency of the output voltage of the inverter. The control circuit, when it is judged that the power system has recovered from the power failure, controls the inverter to change the frequency of the output voltage of the inverter in line with the output frequency pattern, and closes the switch after the phase difference becomes smaller than or equal to a threshold.