Patent classifications
G01R27/14
RESISTIVE-SENSOR INTERFACE
A device to read a variable resistor has an analog to digital converter (ADC), a first switch and a second switch. The ADC has a first ADC input, a second ADC input and an ADC output. The first switch selectively couples a first voltage indicative of a voltage across a first resistance to the first ADC input. The second switch selectively couples a second voltage indicative of a voltage across a second resistance to the second ADC input. The ADC outputs a signal indicative of a value of the second resistance.
RESISTIVE-SENSOR INTERFACE
A device to read a variable resistor has an analog to digital converter (ADC), a first switch and a second switch. The ADC has a first ADC input, a second ADC input and an ADC output. The first switch selectively couples a first voltage indicative of a voltage across a first resistance to the first ADC input. The second switch selectively couples a second voltage indicative of a voltage across a second resistance to the second ADC input. The ADC outputs a signal indicative of a value of the second resistance.
DETERMINING A TEMPERATURE COEFFICIENT VALUE OF A RESISTOR
The present disclosure relates to circuitry for determining a temperature coefficient value of a resistor. The circuitry comprises circuitry for supplying an AC current signal to the resistor, circuitry for measuring a first voltage across the resistor when the AC current signal is supplied; and processing circuitry configured to determine the temperature coefficient value based on the first voltage.
MEASURING SUPERCAPACITOR DEGRADATION DOWNHOLE
A system for use in a wellbore can include a supercapacitor health measurement device including circuitry for determining a capacitance of a supercapacitor that is positionable in the wellbore. The supercapacitor health measurement device can also include circuitry for determining an equivalent series resistance (ESR) value of the supercapacitor. The supercapacitor health measurement device can further include circuitry for transmitting the capacitance and the ESR value. The system can also include a remote device that is positionable aboveground for receiving the capacitance and ESR value.
MEASURING SUPERCAPACITOR DEGRADATION DOWNHOLE
A system for use in a wellbore can include a supercapacitor health measurement device including circuitry for determining a capacitance of a supercapacitor that is positionable in the wellbore. The supercapacitor health measurement device can also include circuitry for determining an equivalent series resistance (ESR) value of the supercapacitor. The supercapacitor health measurement device can further include circuitry for transmitting the capacitance and the ESR value. The system can also include a remote device that is positionable aboveground for receiving the capacitance and ESR value.
System and method for determining the impedance properties of a load using load analysis signals
Various embodiments are described herein for measuring the impedance properties of a load using load analysis signals. In one example embodiment, a transformer is provided which includes at least one primary winding, and at least one secondary winding. The at least one primary winding is coupled in series between a direct-current (DC) power supply and the load. A variable alternating-current (AC) voltage generator is coupled in-series to the at least one secondary winding, and is configured generate at least one load analysis signal for injection into the load. The impedance properties of the load may be determined for different frequencies in the load analysis signals.
Impedance Analyzer Using Square Wave Stimuli
A microcontroller-based system for measuring the impedance of a device under test (DUT) (35) responsive to a square wave stimulus. A clock generator circuit (26) in the microcontroller (20) generates a clock signal at a base clock frequency. A first timer (25) divides down the base clock frequency by a first frequency divisor integer to set the stimulus frequency of a square wave generated by a general purpose input/output (GPIO) function (24), and a second timer (28) divides down the base clock frequency by a second frequency divisor integer to set the sampling frequency of an analog-to-digital converter (ADC) (30). A discrete Fourier transform executed by a processor (22) is used to determine the impedance of the DUT at the stimulus frequency. The first and second integers are selected so that aliased harmonics fall in different DFT bins from the fundamental tone.
Magnetic Sensor Bridge Using Dual Free Layer
The present disclosure generally relates to sensor device, such as a magnetic sensor bridge, that utilizes a dual free layer (DFL) structure. The device includes a plurality of resistors that each includes the same DFL structure. Adjacent the DFL structure is a magnetic structure that can include a permanent magnet, an antiferromagnetic (AFM) layer having a synthetic AFM (SAF) structure thereon, a permanent magnetic having a SAF structure thereon, or an AFM layer having a ferromagnetic layer thereon. The DFL structures are aligned with different layers of the magnetic structures to differentiate the resistors. The different alignment and/or different magnetic structures result in a decrease in production time due to reduced complexity and, thus, reduces costs.
Magnetic Sensor Bridge Using Dual Free Layer
The present disclosure generally relates to sensor device, such as a magnetic sensor bridge, that utilizes a dual free layer (DFL) structure. The device includes a plurality of resistors that each includes the same DFL structure. Adjacent the DFL structure is a magnetic structure that can include a permanent magnet, an antiferromagnetic (AFM) layer having a synthetic AFM (SAF) structure thereon, a permanent magnetic having a SAF structure thereon, or an AFM layer having a ferromagnetic layer thereon. The DFL structures are aligned with different layers of the magnetic structures to differentiate the resistors. The different alignment and/or different magnetic structures result in a decrease in production time due to reduced complexity and, thus, reduces costs.
Battery Cell Resistance Measurement Device and Method
The present invention relates to a battery cell resistance measurement device and method. A battery cell resistance measurement device according to an embodiment of the present invention including: a carrier signal generation module configured to generate a carrier signal of a first frequency and a second frequency different from the first frequency; a resistance unit including a first resistor and a second resistor having a different resistance value from the first resistor; an impedance measurement unit configured to measure an impedance of both ends of a corresponding application target in a state where the carrier signal is applied to any one of the first resistor, the second resistor, and a battery cell; a switching unit configured to selectively connect any one of the first resistor, the second resistor, and the battery cell to the impedance measurement unit; and a control unit configured to calculate an internal resistance of the battery cell based on the impedance value measured by the impedance measurement unit.