An apparatus comprises an integrated circuit that includes an input to receive an electrical input signal from an electronic sensor, wherein the input signal includes a direct current (DC) offset and a varying signal component; a digital-to-analog converter (DAC) circuit configured to subtract the DC offset from the input signal; a programmable gain amplifier (PGA) operatively coupled to the DAC circuit, wherein the PGA circuit is configured to apply signal gain to the varying signal component of the input signal; and a measurement circuit configured to generate a measure of the varying signal component.

An apparatus comprises an integrated circuit that includes an input to receive an electrical input signal from an electronic sensor, wherein the input signal includes a direct current (DC) offset and a varying signal component; a digital-to-analog converter (DAC) circuit configured to subtract the DC offset from the input signal; a programmable gain amplifier (PGA) operatively coupled to the DAC circuit, wherein the PGA circuit is configured to apply signal gain to the varying signal component of the input signal; and a measurement circuit configured to generate a measure of the varying signal component.

A method of impedance measurement of a device under test (DUT) is disclosed based on a random excitation signal, the method comprising the steps of generating the random excitation signal, applying the generated random excitation signal to the DUT through two points of a data acquisition board (DAQ) and re-structuring the converted random excitation signal through a plurality of iterative calibration loops, wherein spectral phase of the random excitation signal is derived from a discrete uniform distribution and its time domain amplitude is controllable. The random excitation signal is a structured Gaussian White Noise (GWN) signal or sequence, which is generated based on the user-defined input parameters such as white noise power level, frequency range between the minimum and maximum frequencies (F.sub.min and F.sub.max), and frequency step (F.sub.step).

A method of impedance measurement of a device under test (DUT) is disclosed based on a random excitation signal, the method comprising the steps of generating the random excitation signal, applying the generated random excitation signal to the DUT through two points of a data acquisition board (DAQ) and re-structuring the converted random excitation signal through a plurality of iterative calibration loops, wherein spectral phase of the random excitation signal is derived from a discrete uniform distribution and its time domain amplitude is controllable. The random excitation signal is a structured Gaussian White Noise (GWN) signal or sequence, which is generated based on the user-defined input parameters such as white noise power level, frequency range between the minimum and maximum frequencies (F.sub.min and F.sub.max), and frequency step (F.sub.step).

Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.

Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.

Systems and methods are provided to determine an internal property of a food product. The system includes one or more analyzing devices, a camera and a central unit in communication with the camera and analyzing device. The analyzing device is configured to analyze an interior region of the food product. The camera is configured to analyze an external property of the food product. The central unit is configured to determine the internal property of the food product based on feedback provided by the analyzing device and the camera.

Systems and methods are provided to determine an internal property of a food product. The system includes one or more analyzing devices, a camera and a central unit in communication with the camera and analyzing device. The analyzing device is configured to analyze an interior region of the food product. The camera is configured to analyze an external property of the food product. The central unit is configured to determine the internal property of the food product based on feedback provided by the analyzing device and the camera.

Embodiments of the disclosure are drawn to apparatuses and methods for testing the resistance of through silicon vias (TSVs) which may be used, for example, to couple multiple memory dies of a semiconductor memory device. A force amplifier may selectively provide a known current along a mesh wiring structure and through the TSV to be tested. The force amplifier may be positioned on a vacant area of the memory device, while the mesh wiring structure may be positioned in an area beneath the TSVs of the layers of the device. A chopper instrumentation amplifier may be selectively coupled to the TSV to be tested to amplify a voltage across the TSV generated by the current passing through the TSV. The chopper instrumentation amplifier may be capable of determining small resistance values of the TSV.

An impedance measuring apparatus is disclosed. The impedance measuring apparatus includes an input current generator configured to generate a sinusoidal input signal of a carrier frequency, a first electrode configured to apply the sinusoidal input signal to an object which has an impedance, a second electrode configured to receive an amplitude modulated signal from the object, a first amplifier configured to amplify the received amplitude modulated signal and output a first amplified signal, a baseline signal subtractor configured to subtract a baseline signal generated based on the first amplified signal from the amplitude modulated signal and output a subtraction modulated signal, an analog-to-digital converter (ADC) configured to convert the subtraction modulated signal to a digital modulated signal, and an impedance measurer configured to measure the impedance based on the digital modulated signal.