A measuring instrument according to an exemplary embodiment includes a base board, at least one sensor chip provided on the base board, and a circuit board provided on the base board. The at least one sensor chip includes a sensor unit including a signal electrode having a front surface intersecting the base board in a radial direction, a guard electrode disposed on a rear side of the signal electrode, and a first ground electrode disposed on a rear side of the guard electrode. The at least one sensor chip includes a second ground electrode extending along a lower surface of the sensor unit. A space between the second ground electrode and the sensor unit is filled with an insulating material.

A capacitance detection method and circuit are provided. The detection method includes: performing charging, base capacitance offsetting, and charge transferring successively on a capacitor to be detected in an i-th first offsetting process of the first offsetting processes, to generate a first output voltage, wherein i≤N; performing discharging, base capacitance offsetting, and charge transferring on the capacitor to be detected successively in a j-th second offsetting process of the second offsetting processes, to generate a second output voltage, wherein j≤M; and determining a capacitance variation of the capacitor to be detected before and after the capacitor to be detected is affected by an external electric field based on the first output voltages corresponding to N first offsetting processes and the second output voltages corresponding to M second offsetting processes in the detection period.

A capacitance detection circuit, a detection chip, and an electronic device are provided. The circuit includes: a first drive module, a conversion module, a processing module, and a control module. The first drive module is configured to charge a first capacitor to be detected. The conversion module is configured to perform charge conversion processing on the first capacitor to be detected to generate an output voltage. The control module is configured to control a first suppression module of the conversion module to suppress an interference signal with a frequency less than a first frequency or greater than a second frequency when the conversion module generates the output voltage, and the second frequency is greater than the first frequency. The processing module is configured to determine a capacitance change before and after the first capacitor to be detected is affected by an applied electric field based on the output voltage.

The present invention discloses a universal connection recognition system which includes a universal connector, a pin recognition module and a signal detection module, wherein the universal connector is composed of plural testing pins that are electrically connected to plural connection pads to be tested, while at least one testing pin is connected to each connection pad to be tested. With the implementation of the present invention, complex production process or equipment is not required thus enormously reduce the implementation cost; the universal connection recognition system can be applied to connections of great diversity of inspection instruments or equipment to thus make more applications possible; and with the learning capability of the universal connection recognition system, any inspection instrument or equipment once connected is memorized to have the capability of achieving automatic and exact pin compatibility when the inspection instrument or equipment is connected again.

The present invention discloses a universal connection recognition system which includes a universal connector, a pin recognition module and a signal detection module, wherein the universal connector is composed of plural testing pins that are electrically connected to plural connection pads to be tested, while at least one testing pin is connected to each connection pad to be tested. With the implementation of the present invention, complex production process or equipment is not required thus enormously reduce the implementation cost; the universal connection recognition system can be applied to connections of great diversity of inspection instruments or equipment to thus make more applications possible; and with the learning capability of the universal connection recognition system, any inspection instrument or equipment once connected is memorized to have the capability of achieving automatic and exact pin compatibility when the inspection instrument or equipment is connected again.

Described is an invention that adds capacitive sensing ability with a single magnetic field sensor location or distributed within an array of surfaces of the sensor. The capacitive sensing can be achieved by modifying a classic Hall effect sensor or putting separate capacitive sensor plates in close proximity to the hall effect sensor.

An inductive alignment system is provided. The system includes a power source providing a forcing function and a first inductor in communication with the power source. The first inductor exhibits a first electrical property in response to the forcing function. The system also includes a second inductor in communication with the first inductor. The second inductor exhibits a second electrical property in response to the forcing function. The system includes a comparator that compares the first electrical property with the second electrical property and generates a signal based at least in part on a deviation between the first electrical property and the second electrical property. The deviation is caused at least in part by inductive coupling between a proximate object and at least one of the first inductor and the second inductor. A method of inductive alignment using the above system is also provided.

An improved detector device for locating studs and other objects behind a substrate (such as a wall) uses one or more light emitting diodes (LEDs) in combination with a photochromic compound to mark the locations on the substrate behind which objects are located.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.