Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

Aspects of the disclosure are directed to a pulse to digital converter. In accordance with one aspect, the pulse to digital converter includes an input to receive an input pulse signal; a fractional element, coupled to the input, wherein the fractional element generates a fractional pulse width measurement of the input pulse signal; and an integral element, coupled to the input, wherein the integral element generates an integral pulse width measurement of the input pulse signal, and wherein the fractional pulse width measurement and the integral pulse width measurement are concatenated as an output signal.

A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a P.sup.th flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

A spot welding method includes supplying a welding current having a pulse-shaped waveform to a workpiece by alternately executing a step of maintaining the welding current within a set peak current range and a step of decreasing the welding current from the peak current range toward a bottom current and then increasing the welding current toward the peak current range when an effective value of the welding current reaches a set target range for a plurality of cycles. The spatter detection method includes measuring a pulse width IW(1), IW(2), . . . in each cycle of the pulse-shaped waveform and detecting the occurrence of spatter when a pulse width difference D(M)=IW(M)IW(M1) between a pulse width IW(M) in a target cycle (M-th cycle) and a pulse width IW(M1) in a cycle immediately before the target cycle exceeds a width threshold value Dth.

A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.

A duty cycle detection circuit may include: a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal.

A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.