A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.

A method of assessing a pulse-width-modulated signal in which the pulse-width-modulated signal to be assessed is applied to a first input of a microcontroller and a signal, that depends on the pulse-width-modulated signal being assessed, is applied to a second input of the microcontroller for assessment. The pulse-width-modulated signal being assessed is applied to a voltage divider to produce the signal that depends on the same. For the pulse-width-modulated signal to be assessed and for the signal that depends on the same, in each case, the microcontroller determines a time interval between signal edges of the respective signal, and the signal is assessed on the basis of a difference between the time interval between the signal edges in the pulse-width-modulated signal to be assessed and the time interval between the signal edges in the signal that depends on the same.

A duty cycle detector (DCD) circuit may include: a duty cycle detector including one or more capacitor sets which are charged, discharged, or charged and discharged a clock, and suitable for detecting a duty cycle of the clock; and a frequency detector suitable for detecting a frequency of the clock. Each of the one or more capacitor sets has an adjustable capacity according to the frequency detection result of the frequency detector.

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

An event-driven transmission method comprises converting at least one event to at least one corresponding pulse pair and transmitting the at least one pulse pair. In this context, a delay between each pulse pair represents a corresponding identifier with respect to the respective event or with respect to at least one corresponding object causing or experiencing the respective event.

A spot welding method includes supplying a welding current having a pulse-shaped waveform to a workpiece by alternately executing a step of maintaining the welding current within a set peak current range and a step of decreasing the welding current from the peak current range toward a bottom current and then increasing the welding current toward the peak current range when an effective value of the welding current reaches a set target range for a plurality of cycles. The spatter detection method includes measuring a pulse width IW(1), IW(2), . . . in each cycle of the pulse-shaped waveform and detecting the occurrence of spatter when a pulse width difference D(M)=IW(M)IW(M1) between a pulse width IW(M) in a target cycle (M-th cycle) and a pulse width IW(M1) in a cycle immediately before the target cycle exceeds a width threshold value Dth.

A method for acquiring a PWM signal includes: acquiring an initial count value during a pulse period of the PWM signal based on an initial frequency division coefficient; determining a predicted frequency of the PWM signal based on the initial count value; determining a corresponding target frequency division coefficient based on the predicted frequency; and acquiring a target count value during the pulse period of the PWM signal and a target count value during a pulse width time of the PWM signal based on the target frequency division coefficient, determining an actual frequency of the PWM signal based on the target count value during the pulse period of the PWM signal, and determining an actual duty ratio of the PWM signal based on the target count value during the pulse period of the PWM signal and the target count value during the pulse width time of the PWM signal.

A high-precision pulse width measurement circuit includes a sampling clock and calibration clock circuit, a sampling circuit, and a calibration circuit. The sampling clock and calibration clock circuit includes a group of delay units and a clock frequency divider, wherein each of the delay units is used for outputting a periodic sampling clock signal HRCLK, and the clock frequency divider is used for generating, according to the sampling clock signal HRCLK, a low-frequency clock signal CALCLK for sampling precision calibration. The sampling circuit, only working in an HRCLK clock domain, includes a counter HRCNT, four capture registers HRCAP1-HRCAP4, an edge detection circuit, and an interrupt control circuit. The calibration circuit includes counters CALCNT and SYSCNT, bit capture registers CALCAP and SYSCAP, a bit register CALPRD and a comparator.

According to a method for filtering measurement data of a sensor system (2), light pulses (5) reflected in the environment of the sensor system (2) are captured by means of an array (7) of optical detectors (8, 9, 10). A multiplicity of measurement signals (11, 12) are generated by means of the array (7) based on the captured light pulses. A computing unit (3) identifies a first measurement signal (11) whose pulse energy is greater than a specified minimum energy, wherein the first measurement signal (11) was generated by a first detector (8). A second measurement signal (12) is compared with the first measurement signal (11) by means of the computing unit (3), wherein the second measurement signal (12) was generated by a second detector (9), which is at a distance from the first detector (8) that is less than or equal to a specified maximum distance. The computing unit discards at least a part of the second measurement signal depending on a result of the comparison.

A compensation circuit includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The resistor-capacitor circuit includes a first resistor-capacitor sub-circuit and a second resistor-capacitor sub-circuit. The first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit are coupled to the control circuit, and operate simultaneously to compute an ON time of a front end module. The control circuit is coupled to the resistor-capacitor circuit, and is used to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and includes an adjustment circuit used to generate a bias signal according to the ON time, and output the bias signal to the front end module.