A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.

A method for monitoring degradation of a flashlamp including triggering the flashlamp to produce a light pulse, monitoring at least one parameter as a function of time to obtain a pulse waveform of the light pulse, comparing the pulse waveform to at least one reference pulse waveform to determine a difference therebetween, and flagging an end-of-lamp-life condition when the difference exceeds a predetermined threshold.

A method for monitoring degradation of a flashlamp including triggering the flashlamp to produce a light pulse, monitoring at least one parameter as a function of time to obtain a pulse waveform of the light pulse, comparing the pulse waveform to at least one reference pulse waveform to determine a difference therebetween, and flagging an end-of-lamp-life condition when the difference exceeds a predetermined threshold.

An occurrence of a first set of n periods of a frequency-shift-keying (FSK)-modulated waveform is counted, where n is an integer number. The n periods of the FSK-modulated waveform in the first set have a first time duration. An occurrence of a second set of n periods of the waveform is counted. The n periods of the waveform in the second set have a second time duration. The first time duration is determined based on the counting of the first set of n periods. The second time duration is determined based on the counting of the second set of n periods. A difference between the first time duration and the second time duration is compared to a threshold. Changes in frequency of the waveform are detected based on the comparing of the difference between the first time duration and the second time duration to the threshold.

A tamper detection circuit comprising a trace antenna, an amplifier comprising an amplifier input terminal coupled to the trace antenna, and a comparator comprising (i) a first comparator input terminal coupled to an output terminal of the amplifier, (ii) a second comparator input terminal coupled to a voltage reference source, and (iii) a comparator output terminal configured to output a pulse signal based on voltage signals received at the first comparator input terminal and the voltage reference source.

A tamper detection circuit comprising a trace antenna, an amplifier comprising an amplifier input terminal coupled to the trace antenna, and a comparator comprising (i) a first comparator input terminal coupled to an output terminal of the amplifier, (ii) a second comparator input terminal coupled to a voltage reference source, and (iii) a comparator output terminal configured to output a pulse signal based on voltage signals received at the first comparator input terminal and the voltage reference source.

An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.

An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.