Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

A method of assessing a pulse-width-modulated signal in which the pulse-width-modulated signal to be assessed is applied to a first input of a microcontroller and a signal, that depends on the pulse-width-modulated signal being assessed, is applied to a second input of the microcontroller for assessment. The pulse-width-modulated signal being assessed is applied to a voltage divider to produce the signal that depends on the same. For the pulse-width-modulated signal to be assessed and for the signal that depends on the same, in each case, the microcontroller determines a time interval between signal edges of the respective signal, and the signal is assessed on the basis of a difference between the time interval between the signal edges in the pulse-width-modulated signal to be assessed and the time interval between the signal edges in the signal that depends on the same.

An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

A ground check system for checking a ground conductor of a power supply comprising at least one line conductor comprises a pulse generator and a compare circuit. The pulse generator applies a test signal to a test circuit formed at least in part by the ground conductor and the at least one line conductor when an AC voltage on the at least one line conductor is approximately zero volts. The compare circuit compares the test signal passing through the test circuit with at least one test criteria indicative of an unacceptable ground.

The present disclosure relates to a partial discharge monitoring system and a partial discharge monitoring method that are capable of monitoring and determining a defect generated in a high-voltage power device in real time by pattern recognizing signals generated from the high-voltage power device with a machine learning algorithm being applied.

A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.

A high-frequency QRS waveform curve analysis method comprises: acquiring a high-frequency QRS waveform curve; selecting the high-frequency QRS waveform curve in a preset time period as a reference waveform curve; selecting a point with the minimum root-mean-square voltage on the reference waveform curve as a first reference point; selecting a second reference point meeting a first selection condition and a third reference point meeting a second selection condition, wherein the time of the first reference point is later than that of the second reference point and earlier than the third reference point; based on the first reference point and the second reference point, determining an amplitude falling relative value; based on the first reference point and the third reference point, determining an amplitude rising relative value. If the amplitude falling rising relative values meet a preset condition, determining reference information according to the high-frequency QRS waveform curve.

A monitor for a node of a time division multiple access (TDMA) data bus comprises a logic device configured to calculate a metric of bandwidth use of the TDMA data bus based on monitored signals transmitted by the node, compare of the metric of bandwidth calculated with an expected metric of bandwidth use for the node, determine that a babbling node failure has occurred in response to the metric of bandwidth calculated exceeding the expected metric of bandwidth use for the node, and issue a control signal to reset the node in response to a detected babbling node failure being determined.

A compensation circuit includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The resistor-capacitor circuit includes a first resistor-capacitor sub-circuit and a second resistor-capacitor sub-circuit. The first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit are coupled to the control circuit, and operate simultaneously to compute an ON time of a front end module. The control circuit is coupled to the resistor-capacitor circuit, and is used to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and includes an adjustment circuit used to generate a bias signal according to the ON time, and output the bias signal to the front end module.

A method is provided for testing switch signals of an inverter of an electric machine of a drive system of a motor vehicle. The electric machine is controlled via a pulse-width modulation generated by a control unit using a target duty cycle and a triangular-waveform voltage sequence. An actual duty cycle of a current pulse-width modulation is continuously ascertained from the switch signals and compared with the target duty cycle of the control unit.