Patent classifications
G01R31/10
Integrated-circuit-level test system and method
The present disclosure provides an integrated-circuit-level (IC-level) test method and system. The IC-level test method includes the operations of: providing, by a stage wagon, a plurality of burn-in boards to an IC loading chamber; determining, by the IC loading chamber, at least one disposing configuration for a plurality of ICs according to at least one docking mechanism of the stage wagon; disposing, by the IC loading chamber, the plurality of ICs on each of the plurality of burn-in boards according to the at least one disposing configuration; providing, by the stage wagon, the plurality of burn-in boards with the plurality of ICs to a test chamber; and performing, by the test chamber, a test function on the plurality of ICs to determine a status of each of the plurality of ICs.
APPARATUS AND METHOD FOR OPERATING ARC SUPPRESSION COIL
An apparatus and a method for operating an arc suppression coil in an electric power network are disclosed. The arc suppression coil is operated off-resonance with respect to a normal state resonance point of the electric power network during normal operation of the electric power network. An indication for an occurrence of an earth fault in the electric power network is received and, in response to the indication, the arc suppression coil is tuned towards resonance with respect to the normal state resonance point, while the earth fault is present in the electric power network.
APPARATUS AND METHOD FOR OPERATING ARC SUPPRESSION COIL
An apparatus and a method for operating an arc suppression coil in an electric power network are disclosed. The arc suppression coil is operated off-resonance with respect to a normal state resonance point of the electric power network during normal operation of the electric power network. An indication for an occurrence of an earth fault in the electric power network is received and, in response to the indication, the arc suppression coil is tuned towards resonance with respect to the normal state resonance point, while the earth fault is present in the electric power network.
Die-to-die connectivity monitoring
An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.
DEVICE AND METHOD FOR MEASURING CHARACTERISTICS OF A WAFER
A device for measuring characteristics of a wafer is provided. The device comprises a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.
Semiconductor testing apparatus for wafer probing testing and final packaged IC testing
During the semiconductor testing process, in order to decrease a temperature difference between a predetermined temperature and a measured temperature, the present disclosure provides a wafer probing testing apparatus and a final testing apparatus for semiconductor testing. The wafer probing testing apparatus comprises a printed circuit board, a probe head, a heater, a thermal sensor and a thermal controller. The final testing apparatus comprises a printed circuit board, a socket, a heater, a thermal sensor and a thermal controller. Due to the arrangement of the thermal sensor, the heater and the thermal controller, the temperature difference of the predetermined temperature may be decreased, and the cost during the semiconductor testing can also be reduced.
Environment control apparatus and chip testing system
An environment control device and a chip testing system are provided. An apparatus body of the environment control device includes a plurality of accommodating chambers. Each of the accommodating chambers has a temperature adjusting device disposed therein. Each of the accommodating adjusting devices includes a temperature adjuster, a contacting structure, a frame body, and an elastic annular enclosed member. When a chip testing device carrying a plurality of chips is disposed in one of the accommodating chambers, and the contacting structure contacts one side of the chips, the elastic annular enclosed member is abutted against the chip testing device, and the chip testing device and the contacting structure jointly define an enclosed space. The temperature adjuster can correspondingly adjust the temperature of the contacting structure so that the chip testing device can perform a predetermined testing process on the chips in a predetermined temperature environment.
REFLECTOMETRY SYSTEM FOR ANALYZING FAULTS IN A TRANSMISSION LINE
A reflectometry system includes an amplifier of the signal to be injected into the cable to be analyzed and that incorporates a mechanism for correcting for the non-linear effect of the amplifier without significantly increasing the bulk of the system by limiting the number of additional components to be incorporated with respect to a system without correction of the non-linear effect.
REFLECTOMETRY SYSTEM FOR ANALYZING FAULTS IN A TRANSMISSION LINE
A reflectometry system includes an amplifier of the signal to be injected into the cable to be analyzed and that incorporates a mechanism for correcting for the non-linear effect of the amplifier without significantly increasing the bulk of the system by limiting the number of additional components to be incorporated with respect to a system without correction of the non-linear effect.
Method of online estimating remaining life of moving power cable
A method is presented to estimate the remaining life of a moving power cable online. The cable is monitored online remotely for further providing suggestions to users for reducing times of power failure and economic loss. An offline AC impedance measurement experiment is designed at first. Three artificial neural networks are established for convert measured impedances into impedances under a baseline context to calculate impedance change ratios. The impedance change ratio indicates the damage of the cable. At last, a remaining margin of the impedance change ratio is figured out online under various contexts with three equations. Thus, the remaining life of the cable is obtained online.