Provided is a deterioration diagnosis system which diagnoses deterioration of an N-phase rotational machine (N denotes a natural number). The deterioration diagnosis system includes a first current sensor to be attached individually to at least lead wires of (N-1)-phases in a rotational machine, the first current sensor being able to detect a current amplitude arising from a plurality of deterioration causes, and a second current sensor to be attached collectively to the lead wires of all phases in the rotational machine, the second current sensor being able to detect a current amplitude arising from a plurality of deterioration causes.

A kit for joining opposing ends of two medium-voltage (between about 3.3 kV and about 52 kV) electrical power distribution cables, comprising an electrically-conductive connector for connecting the conductors of the cables, an electrically-insulating surround material for enveloping the connector, a partial discharge detector, comprising a generally cylindrical, electrically-conductive sheath around the insulating surround, from which an electrically-conductive element extends in an axial direction along the length of at least one of the cables, an outer protective tube for surrounding the remainder of the kit, wherein the conductive element is sufficiently long to project out of the protective tube. A partial discharge detector and a medium voltage cable run are also described.

A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.

A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.

A leak detection system includes a high voltage leak detection (HVLD) testing system configured to inspect a package using a HVLD apparatus that includes an inspection electrode and a detection electrode. The leak detection system includes a grounding system that includes a grounding element. The grounding system is configured to remove, significantly reduce, or conduct away electric charge accumulation on the package. The leak detection system also includes a controller configured to operate and coordinate the operation of the grounding system with the operation of the HVLD testing system.

According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.

According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.

A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

A test apparatus includes a probe card and a tester. The probe card has a plurality of regions corresponding to dies of a wafer, respectively. The probe card includes a tray having a first region with a lens and a second region without a lens. The tester is configured to generate a drive control signal for moving the tray in a first direction or a second direction to locate the first region or the second region at a position facing the dies.

A test apparatus includes a probe card and a tester. The probe card has a plurality of regions corresponding to dies of a wafer, respectively. The probe card includes a tray having a first region with a lens and a second region without a lens. The tester is configured to generate a drive control signal for moving the tray in a first direction or a second direction to locate the first region or the second region at a position facing the dies.