This electrical tree test method is a method for testing for electrical trees in an insulating member including a mica insulation applied to an electrical conductor. The method comprises: an assembly setting step of setting an electrode setting assembly to the outside of the mica insulation; an impregnation step of impregnating the mica insulation with synthetic resin after the assembly setting step; a removal step of removing components of the electrode setting assembly, except an electrode structure, after the impregnation step; a power supply connecting step of connecting, after the removal step, the electrical conductor and the electrode structure to a power supply in order to apply a voltage between the electrical conductor and the electrode structure; and a voltage applying step of applying a voltage between the electrical conductor and the electrode structure, after the power supply connecting step.

This electrical tree test method is a method for testing for electrical trees in an insulating member including a mica insulation applied to an electrical conductor. The method comprises: an assembly setting step of setting an electrode setting assembly to the outside of the mica insulation; an impregnation step of impregnating the mica insulation with synthetic resin after the assembly setting step; a removal step of removing components of the electrode setting assembly, except an electrode structure, after the impregnation step; a power supply connecting step of connecting, after the removal step, the electrical conductor and the electrode structure to a power supply in order to apply a voltage between the electrical conductor and the electrode structure; and a voltage applying step of applying a voltage between the electrical conductor and the electrode structure, after the power supply connecting step.

A system for determining the impact of moisture on a dielectric sealing material may include a testing apparatus having a testing chamber. A dielectric sealing material and a conducting pin may be exposed to the testing chamber. A first electrical lead may be coupled to the conducting pin, and a second electrical lead may be coupled to the dialectic material. An insulation resistance measurement unit may be coupled to both the first electrical lead and the second electrical lead, and the insulation resistance measurement unit may be configured to measure an insulation resistance value between the electrical leads. The insulation resistance measurement unit may measure a first insulation resistance value of the dielectric sealing material in a first environmental condition, and the insulation resistance measurement unit may measure a second insulation resistance value of the dielectric sealing material at a second environmental condition, that is different than the first environmental condition.

A system for determining the impact of moisture on a dielectric sealing material may include a testing apparatus having a testing chamber. A dielectric sealing material and a conducting pin may be exposed to the testing chamber. A first electrical lead may be coupled to the conducting pin, and a second electrical lead may be coupled to the dialectic material. An insulation resistance measurement unit may be coupled to both the first electrical lead and the second electrical lead, and the insulation resistance measurement unit may be configured to measure an insulation resistance value between the electrical leads. The insulation resistance measurement unit may measure a first insulation resistance value of the dielectric sealing material in a first environmental condition, and the insulation resistance measurement unit may measure a second insulation resistance value of the dielectric sealing material at a second environmental condition, that is different than the first environmental condition.

A detection apparatus and an anti-bending device thereof are provided. The detection apparatus includes a probe card circuit board, at least one probe, and the anti-bending device. The probe card circuit board has a first board surface and a second board surface on opposite sides thereof. The at least one probe is mounted on the first board surface. The anti-bending device includes an anti-bending frame, at least one sensor, a processing circuit, and a transmission part. The anti-bending frame is mounted on the second board surface of the probe card circuit board, and the at least one sensor is disposed on the anti-bending frame or the probe card circuit board. The processing circuit is disposed inside the anti-bending frame. The transmission part is mounted on the anti-bending frame, and is electrically coupled to the processing circuit.

The present disclosure discloses an assembly for carrying a chip, and a device and a method for testing a chip. The assembly for carrying a chip is configured to fasten chips of different sizes, and includes a rotatable vertical rod, a cross beam, a first sidewall, and a second sidewall. The rotatable vertical rod is provided with a gear that surrounds the rotatable vertical rod with gear teeth. The cross beam is internally provided with a first through hole and a first chute. A top of the first sidewall is connected to a first connecting rod located in the first chute. A top of the second sidewall is connected to a second connecting rod located in the first chute. A side surface of the first connecting rod is provided with a plurality of first tooth grooves arranged linearly.

A circuit board includes an insulating substrate having a first surface and a second surface opposite to the first surface, a solid conductor located inside the insulating substrate, a first via conductor connected to the solid conductor from a side of the first surface, and a second via conductor connected to the solid conductor from a side of the second surface. The solid conductor has a cutout that intersects a line segment that connects a node of the first via conductor and a node of the second via conductor to each other.

The present disclosure generally relates to a test method and system thereof. The test method comprises: outputting a test control signal to a test power supply of the circuit under test so as to adjust an input signal of the circuit under test so that a gain range of the circuit under test in an abnormal operating state is the same as that of the circuit under test in a normal operating state when the circuit under test enters into the abnormal operating state. The present disclosure may meet requirements for equipment test without sacrificing the efficiency of circuits in normal operating state or adding complexity circuit.

Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows, the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC.