Provided are a failure diagnosis method and apparatus for open circuit failure of a power tube of a three-phase rectifier based on a current signal, relating to a failure diagnosis technique for power electronic equipment and capable of quickly and accurately diagnosing on an open circuit failure of the power tube of the three-phase rectifier without adding a hardware component. The failure diagnosis method only requires a sampled current existing in the control system of the rectifier and some intermediate computing signals and is therefore simple and requires little computing resource. A distorted current after the open circuit failure occurs in the power tube of the rectifier and a positive/negative half cycle where the current is present when the failure occurs serve as diagnostic variables. By analyzing the sampled current, a quick diagnosis on the power tube having the open circuit failure is provided. Thus, the invention is highly applicable.

The present invention relates to a coaxial socket of an impedance matching structure for semiconductor chip testing and a manufacturing method thereof. The coaxial socket includes a test socket locating substrate, a test socket body, a test socket cover, and a test probe. A polymer I and a polymer II are installed and fastened in the test socket body and the test socket cover respectively. A probe slot I and a probe slot II are provided in the polymer I and the polymer II respectively. The test probe is inserted through the probe slot I and the probe slot II. In the present invention, the test socket body and the test socket cover are made of conductive metal, and single-end impedance matching of 50 ohms or differential impedance matching of 100 ohms is performed between them and the probe, to achieve superb signal transmission and heat conduction.

Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.

Low loss high directivity wire couplers use a wire over ground transmission airline structure and a low diameter coaxial cable ending in a wire loop sensor, which is inserted into ground wall of the transmission line leading into a coupled and an isolated port. Higher, capacitively induced, electrical current, because of the confined zone between signal conductor and ground wall, compares favorably with the antiphase magnetically induced current component in the wire loop sensor and leads to increased coupling and directivity over a frequency range up to at least 70 GHz.

An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

Disclosed are a test device and a test method thereof. The test device includes a first electrode, an electron transport unit, a charge generation layer, a hole transport unit and a second electrode which are stacked; the charge generation layer includes an N-type doped layer and a P-type doped layer which is stacked on the N-type doped layer, the N-type doped layer is adjacent to the electron transport unit, and the P-type doped layer is adjacent to the hole transport unit.

A system for glass substrate inspection, such as flat patterned media, includes an air table that holds the glass substrate. The air table includes chucklets that emit gas as air bearings. A camera is disposed over the air table and moves in a direction across a width of a top surface of the glass substrate. An assembly includes a gripper and a probe bar configured to be transported under the camera. The gripper is configured to grip a bottom surface of the glass substrate opposite the top surface. The probe bar delivers driving signals to the glass substrate through a plurality of probe pins.

The present disclosure provides a switching matrix system and an operating method thereof for semiconductor characteristic measurement. The switching matrix system is configured to: detect an assembly of at least one switching matrix module inserted into a plurality of slots of the switching matrix system; determine a user interface according to the assembly of the at least one switching matrix module inserted into the slots, wherein the user interface includes an operable object corresponding to the assembly; and provide the user interface.

A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.

Automatically identifying defect-based test coverage gaps in semiconductor devices includes determining a plurality of apparent killer defects on one or more semiconductor devices with a plurality of semiconductor dies based on characterization measurements of the one or more semiconductor devices acquired by one or more semiconductor fabrication subsystems, determining at least one semiconductor die which passes at least one test based on test measurements acquired by one or more test tool subsystems, correlate the characterization measurements with the test measurements to determine at least one apparent killer defect on the at least one semiconductor die which passes the at least one test, and determining one or more gap areas on the one or more semiconductor devices for defect-based test coverage based on the at least one apparent killer defect on the at least one semiconductor die which passes the at least one test.