A connecting device for inspection includes a probe head configured to hold electric contacts and optical contacts such that tip ends of the respective contacts are exposed on a lower surface of the probe head, and a transformer including connecting wires arranged therein and optical wires penetrating therethrough. The respective proximal ends of the electric contacts and the optical contacts are exposed on an upper surface of the probe head, and tip ends on one side of the connecting wires electrically connected to the proximal ends of the electric contacts and connecting ends of the optical wires optically connected to the proximal ends of the optical contacts are arranged in a lower surface of the transformer. A positional relationship between the tip end of the respective electric contacts and the tip end of the respective optical contacts on the lower surface of the probe head corresponds to a positional relationship between an electrical signal terminal and an optical signal terminal of a semiconductor device.

An electrical characteristic measuring device (70) comprises an evaluation table (30) on which a semiconductor device (10) is to be placed, and a device pressing member (20) to press the device (10). The pressing member (20) comprises a non-conductive electrode pressing part (22) to press a device electrode part (12) and a flange pressing part (23) to press a flange portion (14) of a base material (11). In a flange contact part (42) of the flange pressing part (23), a surface facing the flange portion (14) of the base material (11) has the same shape as a flange facing surface of a screw head of a screw (16) for fastening to an apparatus on which the device 10 is to be mounted. When the device (10) is pressed against the evaluation table (30) by the pressing member (20), the flange pressing part (23) is placed at a position of the base material (11) corresponding to a position of a fastening portion (17) in which a screw insertion groove (15) is included and in which the screw (16) is fastened to the base material (11).

A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

An apparatus may include an upper transparent plate to hold a wafer of bottom-emitting or bottom-detecting optical devices, wherein the upper transparent plate comprises a set of holes in an area of the upper transparent plate for holding the wafer. The apparatus may include a lower transparent plate and a structure supporting the upper transparent plate and the lower transparent plate to form a cavity bounded by the upper transparent plate, the lower transparent plate, and the structure, wherein the structure comprises an opening in fluid communication with the cavity, wherein applying suction through the opening, via the cavity and the set of holes, holds the wafer flat on the upper transparent plate, and wherein an optical path, between a bottom-emitting or bottom-detecting optical device of the bottom-emitting or bottom-detecting optical devices of the wafer and a testing device, passes through the upper transparent plate, the cavity, and the lower transparent plate.

The disclosed technology relates to a method and apparatus for graphically displaying a switching cycle of a switching device. A switching voltage and a switching current are acquired for a device under test via a voltage probe and a current probe, respectively, for a plurality of switching cycles of the device under test. The switching current versus the switching voltage is plotted on a current versus voltage plot as a curve for each of the switching cycles. Each of the curves on the current versus voltage plot overlap each other and are displayed to a user.

A device for processing a multiplicity of semiconductor chips in a wafer assemblage includes an electrically conductive carrier for contacting rear contacts of the semiconductor chips, an electrically conductive film for contacting front contacts of the semiconductor chips that are situated opposite the rear contacts, and a squeegee, which is displaceable relative to the film and is configured to press a region of the film in the direction toward the carrier.

An aging detector for an electrical circuit component and a method for monitoring an aging of a circuit component includes an input of the aging detector recording a parameter of the circuit component, with the aging circuit being configured to, based on the recorded parameter, determine a corresponding response threshold and/or a response or adapt the response threshold and/or the response, and to initiate the response to the parameter exceeding the specific response threshold.

A process and system for testing includes: arranging devices in a temperature-controlled environment; applying a negative gate bias voltage (Vgs) to the devices; applying a drain voltage (Vds) to the devices; measuring currents and/or voltages of the devices to generate device test data; determining a failure of one or more of the devices based on the device test data generated from the device currents and/or the voltages to generate failure data; and outputting the failure data for the of devices.

Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.