Patent classifications
G01R31/2601
SEMICONDUCTOR WAFER WITH PROBE PADS LOCATED IN SAW STREET
A semiconductor wafer comprising a first die including a first integrated circuit having a trimmable or programmable component. The trimmable or programmable component is configured to be trimmed or permanently altered in response to an electrical signal. The semiconductor wafer also includes a saw street arranged adjacent to the first die, and at least one probe pad electrically connected to the trimmable or programmable component. The at least one probe pad is arranged in the saw street.
Semiconductor device and analyzing method thereof
The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V.sub.dd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V.sub.th) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V.sub.ss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.
Method and system for online monitoring of health status of insulated-gate bipolar transistor module
A method and a system for online monitoring of a health status of an insulated-gate bipolar transistor (IGBT) module are provided, which belong to the field of IGBT status monitoring. In order to overcome the inability to real-time monitor health statuses of existing IGBT modules, the method of the disclosure includes the following steps. A current sensor is used to measure a collector current of each IGBT module. A collected current value is substituted into a simulation model to obtain a current imbalance rate. A failure module is located according to the current imbalance rate and temperature to achieve the objective of monitoring an IGBT health status.
CONNECTING DEVICE FOR CONNECTING AN ELECTRICAL DEVICE UNDER TEST TO A TEST INSTRUMENT
A connecting device for electrically connecting signal contact portions of an electrical device under test includes a lower modular unit and an upper modular unit. The lower modular unit includes a port substrate and a plurality of lower connecting terminals electrically connected with the port substrate. The upper modular unit is disposed above the lower modular unit and includes a plurality of upper connecting terminals movable relative to an upper wall. The upper connecting terminals are movable as a result of a downward pressing of the electrical device to the upper modular unit to project outwardly of the upper wall and to electrically connect with the signal contact portions. The upper connecting terminals are electrically connected with the lower connecting terminals.
WAFER METROLOGY TECHNOLOGIES
Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and/or magnetic field biases can be applied to the sample to provide additional information.
Systems and methods for semiconductor adaptive testing using inline defect part average testing
Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
Method for characterizing fluctuation induced by single particle irradiation in a device and application thereof
A method for characterizing a fluctuation induced by single particle irradiation in a device. A plurality of devices varying in size are tested respectively before and after irradiation to obtain threshold voltage distribution, such that a threshold voltage fluctuation induced by irradiation is obtained and used to correct a process fluctuation model, so as to correct a design margin of the devices working under the irradiation.
DEVICE AND METHOD FOR TESTING SEMICONDUCTOR DEVICES
A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.
Lifetime estimating system and method for heating source, and inspection apparatus
A lifetime estimation system for estimating a lifetime of a heating source is provided in an apparatus for heating a target object using the heating source and performing a feedback control of a target object temperature using a temperature controller based on a temperature measurement value of the target object measured by a temperature measuring device. The temperature controller controls a power supplied to the heating source and performs a temperature control using a state space model to perform the feedback control of the temperature of the target object. The lifetime estimation system includes a temperature monitor unit that monitors the temperature measurement value of the target object, a hunting amount detection unit that detects a hunting amount in a stable region of the monitored temperature of the target object, and a lifetime estimation unit that estimates a lifetime of the heating source from the detected hunting amount.
Device for testing components under elevated gas pressure
Disclosed is a device for testing components under elevated pressure in which a pressure chamber is provided. The lateral boundary of the pressure chamber included a ring and an annular part, which may move perpendicularly to the plane of the component to be tested. A velvet-like lining is provided on the end face of the annular part or of the ring that faces the component to be tested. The fibers of the lining protrude from the annular part or from the ring toward the component to be tested and bridge the gap between the device and the component.