Provided are a sampling measurement method and system, computer device and storage medium. The sampling measurement method includes: acquiring a preset measurement ratio of each process element in a process station; acquiring an actual measurement ratio of a process element associated with a lot of products to be measured that arrive at the measurement station in the process station; and, when the actual measurement ratio of the associated process element is less than the corresponding preset measurement ratio, controlling a measurement machine at the measurement station to measure the lot of products to be measured.

A testing circuit includes a first circuit and a second circuit. The first circuit has a first capacitor and a second capacitor. The first circuit is configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor. The second circuit has the first capacitor and the second capacitor. The second circuit is configured to transfer at least a portion of a second voltage across the second capacitor to the first capacitor.

An apparatus for testing an Integrated Circuit (IC) to be installed on a product substrate of a Multi-Chip Module (MCM) is disclosed. The apparatus includes a test substrate including (i) a first surface configured to receive the tested IC and at least an additional IC, (ii) a second surface that is opposite the first surface and is configured to receive electrical contacts, and (iii) first electrical traces for conveying electrical signals between the tested IC, the additional IC and the electrical contacts. The apparatus further includes a second electrical trace, which is formed in the test substrate instead of the additional IC and is configured to electrically connect between two of the first electrical traces.

A testing apparatus includes multiple testing units arrayed in a first axial direction in plan view, the multiple testing units being configured to respectively press probes against electronic devices on chucks to test the electronic devices, multiple gas circulating units respectively disposed in areas each corresponding to one or more testing units among the multiple testing units, the multiple gas circulating units respectively including first fans configured to circulate a gas in the areas along a second axial direction in plan view, multiple temperature detecting units configured to respectively detect temperatures of the chucks, and a controller configured to control drive of the first fans of the multiple gas circulating units based on the detected temperatures of the chucks.

Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and/or magnetic field biases can be applied to the sample to provide additional information.

An operating condition monitor (100) for monitoring an operating condition of a transistor-based power converter (102), comprising: a sensing apparatus (106) configured to measure a turn-off transient energy of the power converter (102), a processor (108) in communication with the sensing apparatus (106) to receive the measurement of the turn-off transient energy, the processor being configured to: compare the measurement of the turn-off transient energy to a threshold; and issue an event signal based on the comparison to the threshold meeting a comparison criterion. A method (200, 200′) of monitoring an operating state of a transistor-based power converter is also disclosed.

A test assembly for testing a device under test includes a probe card assembly and a cap secured to the probe card assembly. The probe card assembly includes a probe tile having a plurality of openings. The probe tile includes a plurality of probe wires including a probe needle portion and a probe tip portion. A seal is disposed on a surface of the probe tile and forms an outer perimeter of a pressurized area. The probe tile includes an insulation layer formed within the pressurized area that is configured to separate the probe needle portion from the device under test. The insulation layer includes an aperture through which the probe tip portion extends to contact the device under test. The cap includes a fluid inlet and a fluid return outlet that are in fluid communication with the plurality of openings of the probe tile.

A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.

The present application provides two-port on-wafer calibration piece circuit models and a method for determining parameters. The method includes: measuring a single-port on-wafer calibration piece circuit model corresponding to a first frequency band to obtain a first S parameter; calculating, according to the first S parameter, an intrinsic capacitance value of a two-port on-wafer calibration piece circuit model corresponding to the single-port on-wafer calibration piece circuit model; measuring the two-port on-wafer calibration piece circuit model corresponding to the terahertz frequency band to obtain a second S parameter; and calculating a parasitic capacitance value and a parasitic resistance value of the two-port on-wafer calibration piece circuit model according to the second S parameter and the intrinsic capacitance value.

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.