An apparatus for testing a semiconductor device is described. The apparatus includes a test chamber in which a test process for a plurality of semiconductor devices is performed, a first storage disposed in the test chamber with a first semiconductor device located therein, a second storage spaced apart in a first direction from the first storage with a second semiconductor device located therein, a first nozzle extending in the first direction on a first sides of the first and second storages and including a plurality of first air outlets configured to discharge air, a second nozzle extending in the first direction on and including a plurality of second air outlets configured to discharge air, and a controller controlling temperatures of the first and second semiconductor devices within a predefined temperature range by controlling the air discharged by the first and second nozzles.

Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG. The physical contacting to the topside of the wafer is noncontaminating and noninvasive to the semiconductor layers.

A safety container for high-power, electronic device testing, the safety container including a first shell and first and second ports in the first shell. The first shell is configured to substantially surround a testing chamber sized to accommodate a device-under-test (DUT). The first shell is substantially rigid. The first port is configured to allow a fluid into the testing chamber, the second port configured to allow the fluid to exit the testing chamber.

A wafer inspection apparatus according to one embodiment is a wafer inspection apparatus including a plurality of inspection parts arranged in a height direction and a lateral direction, and includes a pair of air circulating means disposed at both ends in a longitudinal direction of an air circulating region including the plurality of inspection parts arranged in the lateral direction and configured to circulate air in the circulating region.

One embodiment of the present invention provides a method for evaluating the electrical defect density of a semiconductor layer, which comprises: a step for measuring an electric current by applying a voltage to a semiconductor element 1 which comprises a GaN layer 12 that serves as a semiconductor layer; and a step for deriving the electrical defect density in the GaN layer 12 with use of the measured electric current value.

A cleaning method in an inspection apparatus that performs an electrical characteristic inspection on a device under test formed in an inspection object, includes: transferring, in a transfer process, a stage on which the inspection object is mounted to a position facing a probe card having probes, the probes being brought into contact with the device under test during the electrical characteristic inspection; subsequently, exhausting and depressurizing a space between the probe card and the stage facing the probe card in a peeling-off preparation process; introducing a gas into the space which has been depressurized and peeling off foreign substances adhering to a front surface of the stage and the probes in a foreign substance peeling-off process; and exhausting the space to discharge the foreign substances while continuously introducing the gas into the space in a foreign substance discharging process.

A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

The invention discloses a wafer testing device of flip chip VCSEL for testing a wafer having a plurality of light emitting units. The wafer testing device of flip chip VCSEL comprises a wafer testing carrier and a flexible conductive layer. The wafer testing carrier has a first surface. A plurality of testing portions are disposed on the first surface. The flexible conductive layer, detachably disposed on the first surface, are conductive in vertical direction and insulated in horizontal direction. Wherein the wafer is disposed on the flexible conductive layer, and each light emitting unit is electrically connected with one of the testing portions in vertical direction through the flexible conductive layer while testing the wafer.

A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.

A device may generate, using a random telegraph signal (RTS) noise generator, a simulated RTS noise as input to a transistor included in an electronic circuit. The device may determine, based on the simulated RTS noise input to the transistor, a simulated output signal from the transistor.