G01R31/2642

Method for the characterization and monitoring of integrated circuits

A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Usage metering to prevent IC counterfeit

A timer circuit includes a plurality of n-type field effect transistors (NFETs) powered by a current source, a plurality of electromigration detection elements each electrically connected to a respective NFET of the plurality of NFETs, and a read-out circuit electrically connected to the plurality of electromigration detection elements to meter usage of each of the NFETs.

Temperature control system including contactor assembly

A method for controlling temperature in a temperature control system. The method includes providing a temperature control system including a controller, a first contactor assembly having a first channel system, a plurality of first contacts, each of the first contacts including a portion that is disposed within the first channel system, and one or more of a first exhaust valve or a first inlet valve, and a second contactor assembly having a second channel system, a plurality of second contacts, each of the second contacts including a portion that is disposed within the second channel system, and one or more of a second exhaust valve or a second inlet valve. The method also includes receiving, by the first contactor assembly, a fluid at a first temperature. The method also includes receiving, by the second contactor assembly, the fluid at the first temperature.

Monitoring Semiconductor Reliability and Predicting Device Failure During Device Life
20230280392 · 2023-09-07 ·

A circuit includes one or more sensors formed on one or more dies, each sensor detecting one or more wafer characterization data; a stress generator on the die to control the one or more sensors to place the one or more sensors under stress during wafer manufacturing or operation; and an interface coupled to the one or more sensors to communicate the wafer characterization data to a processor or a tester.

Method and device for wafer-level testing

The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

Circuits and techniques for assessing aging effects in semiconductor circuits

In some examples, a method of operating a circuit may comprise performing a circuit function under normal conditions, performing the circuit function under aggravated conditions, predicting a potential future problem with the circuit function under the normal conditions based on an output of the circuit function under the aggravated conditions, and outputting a predictive alert based on predicting the potential future problem.

Method for characterizing fluctuation induced by single particle irradiation in a device and application thereof

A method for characterizing a fluctuation induced by single particle irradiation in a device. A plurality of devices varying in size are tested respectively before and after irradiation to obtain threshold voltage distribution, such that a threshold voltage fluctuation induced by irradiation is obtained and used to correct a process fluctuation model, so as to correct a design margin of the devices working under the irradiation.

Lifetime estimating system and method for heating source, and inspection apparatus
11796400 · 2023-10-24 · ·

A lifetime estimation system for estimating a lifetime of a heating source is provided in an apparatus for heating a target object using the heating source and performing a feedback control of a target object temperature using a temperature controller based on a temperature measurement value of the target object measured by a temperature measuring device. The temperature controller controls a power supplied to the heating source and performs a temperature control using a state space model to perform the feedback control of the temperature of the target object. The lifetime estimation system includes a temperature monitor unit that monitors the temperature measurement value of the target object, a hunting amount detection unit that detects a hunting amount in a stable region of the monitored temperature of the target object, and a lifetime estimation unit that estimates a lifetime of the heating source from the detected hunting amount.

Semiconductor device reliability evaluation apparatus and semiconductor device reliability evaluation method

A direct-current power supply applies a DC voltage to test semiconductor devices. A current detection unit detects a leakage current of a test circuit in which test semiconductor devices are included. A measuring instrument records a pulse waveform of the leakage current. An analyzer analyzes reliability of test semiconductor devices included in the test circuit based on the recorded pulse waveform.

METHOD AND DEVICE FOR WAFER-LEVEL TESTING
20230366925 · 2023-11-16 ·

The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.