Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

The present disclosure provides examples of methods and systems for estimating an operational state of a semiconductor chip of a power semiconductor device which are based on determining a parameter indicative of an operational state of the semiconductor chip including an indication of uncertainty of the operational state based on the received operational data. The present disclosure further provides examples of methods and systems for predicting remaining useful life of a semiconductor chip.

A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.

Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

An aspect relates to an apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.

Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Systems and methods for improving substrate fabrication are provided. Subsets of dies of substrates may be inspected at various points in the fabrication process to generate spectra data. The spectra data can be used to generate data that are input to a machine learning model to predict yields for the substrates.

The invention discloses a method and a system for characterizing IGBT module aging based on Miner theory, including first establishing a life prediction model with a junction temperature fluctuation T.sub.jm and an average junction temperature ΔT.sub.j as inputs; then measuring a chip junction temperature data of an IGBT module; recording the junction temperature fluctuation T.sub.jm and the average junction temperature ΔT.sub.j of each power cycle; performing one life prediction in each cycle; and taking a reciprocal of a predicted life corresponding to each cycle and adding them to obtain an aging characteristic parameter D of the IGBT module. The invention may more suitably characterize the aging degree of the IGBT, and has the advantages of monotonically increasing change trend and high resolution.