G01R31/2644

SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, METHOD OF PERFORMING INSPECTION ON SEMICONDUCTOR WAFER, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE

A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.

METHOD OF DETECTING FAILURE OF A SEMICONDUCTOR DEVICE

A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.

WAFER ASSEMBLY AND METHOD FOR PRODUCING A PLURALITY OF SEMICONDUCTOR CHIPS
20240096681 · 2024-03-21 ·

Embodiments provide a wafer assembly including a plurality of semiconductor chips, wherein each semiconductor chip has a first main face and a second main face opposite the first main face, and wherein a first electrical contact is disposed on the second main face, a plurality of electrically conducting posts, wherein each first electrical contact is in direct contact with an electrically conducting post, and an electrically insulating sacrificial layer having passages in which the electrically conducting posts are disposed.

Power semi-conductor module, mask, measurement method, computer software, and recording medium
11927619 · 2024-03-12 · ·

Power semi-conductor module (1) comprising: at least one IGBT with a Gate G forming a first electrode (11) and an Emitter E forming a second electrode (12), or at least one MOSFET with a Gate G forming a first electrode (11) and a Source S forming a second electrode (12). The first electrode (11) includes a polysilicon material made in one piece. The one-piece is made partly of a monitoring portion (13). The monitoring portion (13) is in electrical contact with the second electrode (12) such that a leakage current flows between the first electrode (11) and the second electrode (12) in an operational state of the module (1). The monitoring portion (13) has a location, a form, a size and a material composition selected together such that to have a variable resistance in function of its temperature during the operational state of the module (1).

Gyroscope with self-test
11920931 · 2024-03-05 · ·

A microelectromechanical gyroscope which comprises one or more Coriolis masses driven by a drive transducer and a force-feedback system. The force-feedback circuit comprises first and second sideband modulators and the self-test circuit comprises first and second sideband demodulators.

METHOD FOR PREDICTING FAILURE OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

Main cells that constitute a semiconductor element having a trench gate structure include first cells, and second cells having a structure in which gate insulating films are more easily broken by energization than those in the first cells, and the number of which is smaller than that of the first cells. At a time of driving the semiconductor element, a common gate drive voltage is applied to gate electrodes of the first cells and the second cells. An electrical characteristic is measured to detect failure of the second cells due to energization at the time of driving. The gate electrodes of the failed second cells are electrically isolated from the gate electrodes of the first cells so that the gate drive voltage is not applied to the failed second cells. The failure of the first cells is predicted based on the failure of the second cells.

Image sensor with test region
10481196 · 2019-11-19 · ·

An image sensor includes a pixel array and a test region adjacent to the pixel array. Each of the pixel array and the test region include a plurality of pixels, and each of the pixels in the test region include: a substrate including a photoelectric conversion element; and a transparent layer formed over the substrate and having an inclined top surface.

DISPLAY DEVICE
20190348357 · 2019-11-14 ·

A display device including a display panel having panel pad units including a first panel pad unit having first pads arranged in a first column and a second panel pad unit having second pads arranged in a second column; a first member coupled to at least one of the first and second panel pad units; and a second member coupled to the first member and including a plurality of test pads, and wherein the first member includes lines electrically connecting a respective one of the plurality of test pads with a respective one of the first and second pads.

NITRIDE SEMICONDUCTOR EPITAXIAL STACK STRUCTURE AND POWER DEVICE THEREOF
20190341479 · 2019-11-07 ·

A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layerthe first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second average Al composition ratio of the second superlattice epitaxial structure.

INSULATOR APPLIED IN A PROBE BASE AND THE PROBE BASE

An insulator applied in a probe base including a probe mounting hole, the insulator is a sheet structure having plural through holes, and the probe mounting hole is formed at the center of the insulator, and the probe mounting hole and the through hole penetrate from a first surface to a second surface of the insulator, and the regions of the first and second surfaces without the probe mounting hole and the through hole are coplanar. The probe base has a base body and at least a composite assembly, and the base body has at least a testing zone, and the composite assembly is installed in the testing zone and has at least a probe hole for installing a probe, and the insulator is installed into the probe hole.