A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.

A semiconductor device with at least one embedded photodetector is disclosed. The at least one photodetector is embedded in a hot carrier injection (HCI) area, and detects a quantity of emitted photons. Further, the photodetector triggers a warning when the photodetector detects a number of photons greater than a threshold number of photons. Additional embodiments are directed to a method of detecting HCI. The method includes embedding a photodetector in a power semiconductor device, setting at least one threshold number of photons, detecting photons, determining a number of photons, determining when the number of photons is above a threshold number of photons, and generating a warning. When the number of photons is above the threshold, the warning is triggered. Further embodiments are directed to an article of manufacture comprising at least one semiconductor device with at least one photodetector embedded in an area predicted to experience HCI.

A layout for a vertical-cavity surface-emitting laser (VCSEL) is provided. In an example embodiment, the layout comprises a VCSEL, an etched shape around a mesa of the VCSEL, a signal contact layer deposited on section of the mesa, and a ground contact layer. The ground contact layer comprises three parts and is positioned around a first section of the etched shape. The first part of the ground contact layer is deposited on a second section of the etched shape. The second and third parts of the ground contact layer comprise two legs off of the first part. The two legs are symmetrically positioned about two sides of the signal contact layer to form a ground-signal-ground configuration.

Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

A semiconductor device includes a bus, first and second bus drivers that drive the bus, and a control circuit that controls the first and second bus drivers. The control circuit controls the first and second bus drivers in such a way that the first and second bus drivers supply logic signals different from each other to the bus.

A method of manufacturing a semiconductor device is provided. The method includes forming a conductive probe plug on an exposed portion of a die pad of a semiconductor die by way of an electroless plating process. A top surface of the conductive probe plug extends above a top surface of a top passivation layer of the semiconductor die. A copper pillar is formed over the conductive probe plug by way of an electrolytic plating process. Outer sidewalls of the copper pillar surround the top surface of the conductive probe plug. A top surface of the copper pillar is plated with a solder plate material and reflowed to form a solder cap on the top of the copper pillar.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area and die areas. The die areas are separated by the scribe line area. The test structure is disposed in the scribe line area. The test structure includes an isolation feature, a first transistor test device, a second transistor test device. The isolation feature is located in the substrate. The first transistor test device and the second transistor test device are disposed on opposite sides of the isolation feature. Channels of the first transistor test device and the second transistor test device have the same conductivity type. A first gate electrode of the first transistor test device and a second gate electrode of the second transistor test device have opposite conductivity types.

Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.

Embodiments relate to systems and methods for sensor self-diagnostics using multiple signal paths. In an embodiment, the sensors are magnetic field sensors, and the systems and/or methods are configured to meet or exceed relevant safety or other industry standards, such as SIL standards. For example, a monolithic integrated circuit sensor system implemented on a single semiconductor ship can include a first sensor device having a first signal path for a first sensor signal on a semiconductor chip; and a second sensor device having a second signal path for a second sensor signal on the semiconductor chip, the second signal path distinct from the first signal path, wherein a comparison of the first signal path signal and the second signal path signal provides a sensor system self-test.

A testkey structure including the following components is provided. A fin structure is disposed on a substrate and stretches along a first direction. A first gate structure and a second gate structure are disposed on the fin structure and stretch along a second direction. A first common source region is disposed in the fin structure between the first gate structure and the second gate structure. A first drain region is disposed in the fin structure at a side of the first gate structure opposite to the first common source region. A second drain region disposed in the fin structure at a side of the second gate structure opposite to the first common source region. A testkey structure is symmetrical along a horizontal line crossing the first common source region. The present invention further provides a method of measuring device defect or connection defect by using the same.