A power semiconductor module including at least first and second power semiconductor elements, includes a first terminal, a first gate terminal, a second terminal, a second gate terminal, a third terminal and a common terminal. The first terminal connected to a first electrode of the first power semiconductor element. The first gate terminal connected to a gate of the first power semiconductor element. The second terminal connected to a first electrode of the second power semiconductor element. The second gate terminal connected to a gate of the second power semiconductor element. The third terminal connected to a second electrode of the first power semiconductor element and a second electrode of the second power semiconductor element. The common terminal that is connected to the first gate terminal through a first resistor and is connected to the second gate terminal through a second resistor.

A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.

Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.

At least one embodiment of the present disclosure provides a display substrate motherboard, a display substrate, a fabrication method thereof and a display device. The display substrate motherboard includes at least one display substrate unit, the display substrate unit includes a display region, a bonding region and a detection region, the bonding region is located on a side of the display region and the detection region is located on a side of the display region different from the bonding region and configured to detect the display substrate unit.

Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.

The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.

The present disclosure provides an RF power device including: a single RF power transistor; a pad spaced apart from the single RF power transistor and configured to transmit a temperature and RF characteristic information of the single RF power transistor to an outside; and a temperature and RF characteristic detector connected between the pad and the ground and configured to detect the temperature and the RF characteristics of the single RF power transistor, and is characterized in that the ground is connected to the single RF power transistor, and the single RF power transistor, the pad, and the temperature and RF characteristic detector are manufactured on the same wafer.

A semiconductor device and a method for detecting cracks are provided. The semiconductor device includes a first conductive layer, a second conductive layer positioned above the first conductive layer, an isolation layer positioned between the first conductive layer and the second conductive layer, and a transistor electrically coupled to the first conductive layer. The first conductive layer, the second conductive layer, the insulating layer, and the transistor together form a crack detecting structure.

A semiconductor structure for inspection includes a semiconductor plate having a first main surface on one side and a second main surface on the other side, an inspection region provided in the first main surface, a main surface electrode having a first hardness and covering the first main surface in the inspection region, and a protective electrode having a second hardness which exceeds the first hardness, covering the main surface electrode in the inspection region, and forming a current path between the second main surface and the protective electrode via the semiconductor plate.