Patent classifications
G01R31/265
WAFER METROLOGY TECHNOLOGIES
Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and/or magnetic field biases can be applied to the sample to provide additional information.
Method of measuring Fe concentration in p-type silicon wafer
Provided is a method of measuring the Fe concentration in a p-type silicon wafer by the SPV method, by which the detection limit for the Fe concentration can be lowered, and the measurement can be performed in a short time. The measurement by the SPV method is performed in a measurement mode in which irradiation with a plurality of lights having mutually different wavelengths is performed during the same period under conditions where (i) Time Between Readings is 35 ms or more and 120 ms or less and Time Constant is 20 ms or more, or Time Between Readings is 10 ms or more and less than 35 ms and Time Constant is 100 ms or more, and (ii) Number of Readings is 12 times or less.
Method and device for measurement of a plurality of semiconductor chips in a wafer array
A method and a device for measuring a plurality of semiconductor chips in a wafer array are disclosed. In an embodiment a method for measuring the semiconductor chips in a wafer array, wherein the wafer array is arranged on an electrically conductive carrier so that in each case back contacts of the semiconductor chips are contacted by the carrier, wherein a contact structure is arranged on a side of the wafer array facing away from the carrier, and wherein the contact structure includes a contact element and/or a plurality of radiation-emitting measurement semiconductor chips, includes applying a voltage between the contact structure and the carrier and measuring the semiconductor chips depending on a luminous image which is generated by emitted radiation which is caused simultaneously by fluorescence when the semiconductor chips are illuminated or by a radiation-emitting operation of the measurement semiconductor chips when the voltage is applied.
TEST CIRCUIT AND METHOD
A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
TEST CIRCUIT AND METHOD
A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
FIELD-BIASED SECOND HARMONIC GENERATION METROLOGY
Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and/or magnetic field biases can be applied to the sample to provide additional information.
Optical inspection apparatus
An optical inspection apparatus includes a stage that supports a target substrate, the target substrate including a plurality of light emitting elements, a jig that applies an electrical signal to the target substrate, the jig including a regulation resistor, a microscope that generates magnified image data of the target substrate, a camera that captures the magnified image data to generate a color image of the target substrate, and an optical measurement unit that captures the magnified image data of the target substrate to generate a spectrum image and measure optical characteristics of the target substrate.
SUBSTRATE INSPECTION DEVICE AND SUBSTRATE INSPECTION METHOD
Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates.
A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.
Non-contact method to monitor and quantify effective work function of metals
An example semiconductor wafer includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, and a layer of the metal disposed on the dielectric layer. An example method of determining an effective work function of a metal on the semiconductor wafer includes determining a surface barrier voltage of the semiconductor wafer, and determining a metal effective work function of the semiconductor wafer based, at least in part, on the surface barrier voltage.
Method of evaluating insulated-gate semiconductor device
A method of evaluating an insulated-gate semiconductor device having an insulated-gate structure including a channel formation layer made of a wide-bandgap semiconductor and a gate insulating film formed contacting the channel formation layer includes removing the gate insulating film in order to expose a surface of the channel formation layer; taking a phase image of the exposed surface of the channel formation layer using a phase mode of an atomic force microscope; evaluating a surface condition of the exposed surface of the channel formation layer by calculating an evaluation metric from phase shift values in the phase image and by determining whether the evaluation metric satisfies a prescribed condition; and determining that the insulated-gate semiconductor device is acceptable when the evaluation metric satisfied the prescribed condition.