An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of reference chips with respect to the substrate in the images, obtaining relative offsets of subordinate chips with respect to the reference chips in the images, and calculating misalignments of the chips based on the absolute offsets and the relative offsets.

A method for identifying cracks in non-planar substrates is herein disclosed. Images of a substrate in a relaxed state are captured and assessed to identify cracks, if any. Assessment may be conducted optically using broad band illumination, laser illumination, or infrared illumination. Mechanisms for carrying out the method are also disclosed.

An inspection apparatus includes a tester unit that applies a stimulus signal to a semiconductor apparatus, an MO crystal arranged to face a semiconductor apparatus, a light source that outputs light, an optical scanner that irradiates the MO crystal with light output from light source, a light detector that detects light reflected from the MO crystal arranged to face the semiconductor apparatus D and outputs a detection signal, and a computer that generate phase image data based on a phase difference between a reference signal generated based on a stimulus signal and the detection signal, the phase image data including a phase component indicating the phase difference, and generates an image indicating a path of a current from the phase image data.

One or more semiconductor wafers or portions thereof are scanned using a primary optical mode, to identify defects. A plurality of the identified defects, including defects of a first class and defects of a second class, are selected and reviewed using an electron microscope. Based on this review, respective defects of the plurality are classified as defects of either the first class or the second class. The plurality of the identified defects is imaged using a plurality of secondary optical modes. One or more of the secondary optical modes are selected for use in conjunction with the primary optical mode, based on results of the scanning using the primary optical mode and the imaging using the plurality of secondary optical modes. Production semiconductor wafers are scanned for defects using the primary optical mode and the one or more selected secondary optical modes.

Embodiments relate to functional test methods useful for fabricating products containing Light Emitting Diode (LED) structures. In particular, LED arrays are functionally tested by injecting current via a displacement current coupling device using a field plate comprising of an electrode and insulator placed in close proximity to the LED array. A controlled voltage waveform is then applied to the field plate electrode to excite the LED devices in parallel for high-throughput. A camera records the individual light emission resulting from the electrical excitation to yield a function test of a plurality of LED devices. Changing the voltage conditions can excite the LEDs at differing current density levels to functionally measure external quantum efficiency and other important device functional parameters.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and/or magnetic field biases can be applied to the sample to provide additional information.