A method includes providing a detector disposed above a semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector, rotating the stage; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.

A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

A system for testing thermal response time of an uncooled infrared focal plane detector array and a method therefor is provided. The system comprises: a blackbody, a chopper, a detector unit under test and a testing system. The method comprises: emitting radiation by the blackbody, chopping by the chopper, then radiating the radiation to the uncooled infrared focal plane detector array under test; generating different responses on the radiation at different chopping frequencies by the uncooled infrared focal plane detector array under test; collecting different response values of the uncooled infrared focal plane detector array under test at different chopping frequencies; obtaining response amplitude at a corresponding frequency in a frequency domain by FFT; fitting according to a formula $\mathrm{Rv}\left(f\right)=\frac{\mathrm{Rv}\left(0\right)}{\sqrt{1+{\left(2f\right)}^2}}$
to obtain the thermal response time.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

A fault detector for an anti-parallel thyristor includes: a power supply unit configured to supply power to the first and second thyristors; a first current sensor configured to output a first current measurement value that flows through the first thyristor; a second current sensor configured to output a second current measurement value that flows through the second thyristor; and a detector which notifies a fault of a thyristor when the first and second current measurement values satisfy a set fault condition.

A fault detector for an anti-parallel thyristor includes: a power supply unit configured to supply power to the first and second thyristors; a first current sensor configured to output a first current measurement value that flows through the first thyristor; a second current sensor configured to output a second current measurement value that flows through the second thyristor; and a detector which notifies a fault of a thyristor when the first and second current measurement values satisfy a set fault condition.

A method for inspecting a semiconductor device structure is provided. The method includes receiving a semiconductor device structure having a to-be-inspected feature. The semiconductor device structure has a first surface and a second surface. The method also includes applying a polymer-containing solution over the first surface of the semiconductor device structure. The method further includes disposing a transparent substrate over the first surface of the semiconductor device structure and the polymer-containing solution. In addition, the method includes irradiating the polymer-containing solution with a light to form an adhesive layer between the transparent substrate and the semiconductor device structure. The adhesive layer bonds the transparent substrate and the semiconductor device structure. The method also includes inspecting the to-be-inspected feature.

A method for inspecting a semiconductor device structure is provided. The method includes receiving a semiconductor device structure having a to-be-inspected feature. The semiconductor device structure has a first surface and a second surface. The method also includes applying a polymer-containing solution over the first surface of the semiconductor device structure. The method further includes disposing a transparent substrate over the first surface of the semiconductor device structure and the polymer-containing solution. In addition, the method includes irradiating the polymer-containing solution with a light to form an adhesive layer between the transparent substrate and the semiconductor device structure. The adhesive layer bonds the transparent substrate and the semiconductor device structure. The method also includes inspecting the to-be-inspected feature.

Methods and systems are presented for analyzing semiconductor materials as they progress along a production line, using photoluminescence images acquired using line-scanning techniques. The photoluminescence images can be analyzed to obtain spatially resolved information on one or more properties of said material, such as lateral charge carrier transport, defects and the presence of cracks. In one preferred embodiment the methods and systems are used to obtain series resistance images of silicon photovoltaic cells without making electrical contact with the sample cell.

A system and method for rotary motion with vacuum sealing is provided. The system includes a vacuum chamber, a component mount disposed in the vacuum chamber, and a base. A bellows is disposed between the base and the component mount, and the bellows provides a seal between the base and the component mount. The bellows, the base, and the component mount define an actuator compartment therebetween. An actuator is disposed in the actuator compartment. The actuator is configured to rotate the component mount relative to the base in order to align a component disposed on the component mount. Rotation of the component mount relative to the base causes torsional elastic deformation of the bellows.